【灿芯半导体】急招模拟，数字，版图工程师

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灿芯半导体（上海）有限公司，成立于2008年7月，是一家ASIC设计服务公司。公司定位于130/90nm以下的高端设计服务与Turn-Key 服务，为客户提供从源代码或网表到芯片成品的一条龙服务。
灿芯半导体由中芯国际集成电路制造有限公司，以及来自于海外和中国的风险投资公司共同创建。其中中芯国际是世界领先的集成电路晶圆代工企业之一，也是中国内地规模最大、技术最先进的集成电路晶圆代工企业，拥有先进的制造技术，为灿芯半导体提供强大的技术支持和流片保证。
基于客户至上的宗旨和灵活多样的服务理念，灿芯半导体致力于为客户提供完整的芯片整体解决方案，这个方案涵盖了晶圆厂家的选择、工艺节点的应用、IP的提供、后端设计、封装和测试方案与逻辑等方面。灿芯半导体在客户设计的早期就开始参与，并与客户进行充分沟通，从而保证在设计初期就对整个产品有一个全局的把握。更重要的是，灿芯半导体还有一整套严谨的设计流程，该流程从网表开始就进行了严格的质量把关，以保证芯片能够一次流片成功。此外，无论是MPW还是工程试生产，灿芯半导体都能提供测试程序开发和封装设计开发的服务，以满足客户对芯片进度和质量的要求。

与此同时，灿芯半导体还和世界各大晶圆厂商、IP供应商、封装厂商和测试厂商都保持着良好的关系，能够为客户提供多样化的选择。

简历请联系 peter.zhou@britesemi.com  

Senior Analog Design Engineer

Job Requirements:

1.
At least 3 or more years of analog circuit design experience with MS in EE or Physics (more senior levels will also be considered)

2.
Willing to work as an active team player with group’s goal in mind.

3.
Familiar with SPICE simulations including Monte-Carlo analysis

4.
Strong knowledge in physical layout and component’s parasitic effects.

5.
Knowledge with process and device physics is a plus

6.
Acceptable communication skill in written and spoken English

7.
Strong passion to learn

Job Descriptions:

1.
Will work on the following analog IPs but not limit to: ADC/DAC, LDO/DCDC, POR, BOR, Band-gap, various amplifiers, PLL/DLL, HDMI/LVDS, Serdes and high speed interface design

2.
Be responsible for schematic capture, simulation, test plan, DK generation and bench verification/characterizations.

3.
Escort and instruct layout designers
to complete physical implementations

4.
Ensure database integrity before any release.

5.
Execute any project assignment in the timing manner.

6.
Follow company’s quality standards during any project execution.

Senior Digital Design Engineer

Job Requirements:

1.
At least 3 or more years of RTL level digital design experience with MS in EE or related (more senior levels will also be considered)

2.
Willing to work as an active team player with group’s goal in mind.

3.
Experience in writing simple digital models or real number models for analog IPs

4.
Knowledge with process and device physics is a plus

5.
Acceptable communication skill in written and spoken English

6.
Strong Passion to learn

Job Descriptions:

1.
Provide digital design support to complete mixed signal IP.

2.
Perform mixed-signal co-simulations to ensure accurate block level functionality with integrated analog circuits.

3.
Logic Synthesis, Static Timing Analysis and Logic Equivalency Checking

4.
Design for test, scan insertion, ATPG, Functional Test Vectors

5.
Interface with Place and Route Engineering to perform
timing check and back-annotated simulations.

6.
Ensure database integrity before any release.

7.
Execute any project assignment in the timing manner.

8.
Follow company’s quality standards during any project execution.

Analog Layout Engineer

Job Requirements:

1.
At least 2 or more years of custom layout in sub-micron CMOS processes with BS in EE or related

2.
Willing to work as an active team player with group’s goal in mind.

3.
Familiar with Cadence Layout environment and Mentor’s verification flow

4.
HV CMOS  and BCD layout experience is a plus

5.
Knowledge with process and device physics is a plus

6.
Automatic P&R experience is also a plus.

7.
Good communication skill.

8.
Strong Passion to learn

Job Descriptions:

1.
Provide floor plan before any new project starts

2.
layout support for completing mixed signal IP according to schedule.

3.
Perform DRC and LVS check and debug discrepancies.

4.
Perform parasitic extractions

5.
Interface with backend
engineering to ensure accurate IP placement and connections.

6.
Ensure database integrity before any release.

7.
Execute any project assignment in the timing manner.

8.
Follow company’s quality standards during any project execution.