------FPGA接收来自DSP发送的每一位数据,并进行32位移位打包成32位数据包rcv_buf-----------
rcv :process(clk)
begin
if(clk'event and clk = '1')then
if(CLKR_rr ='1' and CLKR_r = '0')then
rcv_buf(0) <= DR;
rcv_buf(31 downto 1) <= rcv_buf(30 downto 0);
end if;
end if;
end process;
-----根据每个帧同步下降沿来把 rcv_buf的值给总线端口------------
Data_latch :process(clk)
begin
if(clk'event and clk = '1')then
if(FSR_rr='1' and FSR_r = '0')then --帧同步下降沿检测
Mcbsp_Data <= rcv_buf; --移位后的32位数据送给端口
end if;
end if;
end process;