ASIC Verification Engineer(上海展讯)

z512v

职位描述：(email:    z512v@hotmail.com) Responsibilities: The candidate will be responsible for building up verification environment and completing logic verification. Qualifications:  Proficiency in logic verification.  Experience with Verilog logic design language.  Experience with high-level verification languages such as System Verilog, Vera, System C or Specman e language.  Experience with UNIX/Linux simulation tools such as NC-Verilog or VCS.  Experience with C and C++ is a plus.  Experience with C_SHELL, TCL or PERL is a plus.  Good knowledge of SOC design is a plus.  Good knowledge of software design is a plus.  Self-motivated and good team player.  MSEE or above, with 2 years experience

yxxjtu

垃圾公司，别去了。。。。坑爹的公司。我刚从那家公司设计部出来。。。。。