2. the first stage has larger gain for less noise and offset, and the second stage has larger current for better driving capability, current up->gain down
3. it depends on CL
5. mobiity of hole< that of electron, depletion PMOS is the best, since the channel is much deeper
6. missmatch of input pair, missmatch of the active load and the systematic offset. all the offset can be equivalent to the input offset, of which the systematic offset can be solved by circuit design, and the other two can only be reduced by good layout match |
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发表于 2009-2-20 13:58:05
