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Title: Senior design engineer-前端设计
Position Description: •In charge ofIP and SOC logic design, verification and Implementation. •Daily dutiesinclude: Digital IC micro-architecture, RTL coding, Logic Synthesis, FunctionVerification, DFT, and Static Timing Analysis. •HDL languageKnowledge, like verilog or vhdl is necessary. •C/C++/perl/tcl/csh/python,UNIX, Linux experience are plus. •Excellentanalytical and problem-solving skills. Quick learner-able to learn and applytechnical and complex topics. •Excellentcommunication skills and the uncanny ability in a cooperative team environmentare required. •Self-motivated,result-oriented, can take ownership and follow-through on tasks. Position Requirements: Essential Qualifications: •Master degreeor above •Major inMicro-electronics, Electronic Engineering, Computer Science, InformationTechnology or equivalent •Ability towork effectively alone or as well as in the team. •Essentialthat the individual demonstrates strong communication, verbal and written •Requiresgood communication skills in English. Desirable Qualifications: •Good at anyfollowing skill sets: ASIC design, FPGA design, Computer architecture, SOCdesign based on ARM/MIPS. •Experienceof DDR If you have interest, PLS send your update CV to zhangyl@cadence.com |