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 楼主 |
发表于 2015-8-24 19:24:24
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.lib device 
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* 0.35um Logic Salicide Dual-gate Process with PLDD structure - Thin gate NMOS transistor without DNWell 
 
.subckt nmos_3p3 d g s b w=0 l=0 
+ as=0 ad=0 ps=0 pd=0 nrd=0 nrs=0 par=1 dtemp=0 
 
m0 d g s b nmos_3p3 w=w l=l as=as ad=ad ps=ps pd=pd nrd=nrd nrs=nrs dtemp=dtemp 
.model nmos_3p3 NMOS 
+Level= 53 
*+lmin=3.5e-7 lmax=1.0e-5 wmin=4.0e-7 wmax=2.0e-5 
+Tnom=25.0 
+version =3.3  hspver=98.2  paramchk=1 
*+Tox= 7.69E-09 
*+Toxm= 7.69E-09 
+Tox= toxn_tn 
+Toxm= toxn_tn 
+Xj= xjn_tn 
+xl= xln_tn 
+xw= xwn_tn 
+Nch= 2.0857000E+17 
+lln= 1.0000000 
,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, 
.ends nmos_3p3 
.......... 
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* 0.35um Logic Salicide Dual-gate Process with PLDD structure - Thin gate NMOS transistor without DNWell 
.subckt nmos_3p3 d g s b w=0 l=0 
+ as=0 ad=0 ps=0 pd=0 nrd=0 nrs=0 par=1 dtemp=0 
 
+ par_vth_tnn=0.0121 
+ par_k_tnn= 0.0136 
+ par_l_tnn= 0 
+ par_w_tnn= 0 
+ par_leff_tnn = 'l - par_l_tnn' 
+ par_weff_tnn = 'par*(w - par_w_tnn)' 
+ p_sqrtarea_tnn = 'sqrt((par_leff_tnn)*(par_weff_tnn))' 
+ var_k_tnn= '0.7071 * par_k_tnn* 1e-06 / p_sqrtarea_tnn' 
+ var_vth_tnn='0.7071*par_vth_tnn* 1e-06 / p_sqrtarea_tnn' 
 
+ mis_k_tnn = agauss (0, var_k_tnn, 1) 
+ mis_vth_tnn = agauss (0, var_vth_tnn, 1) 
+ std_u0n_tn='1-mis_k_tnn*sw_stat_mismatch' 
+ mis_vthon_tn='mis_vth_tnn*sw_stat_mismatch' 
 
m0 d g s b nmos_3p3 w=w l=l as=as ad=ad ps=ps pd=pd nrd=nrd nrs=nrs dtemp=dtemp 
 
.model nmos_3p3 NMOS 
+Level= 53 
*+lmin=3.5e-7 lmax=1.0e-5 wmin=4.0e-7 wmax=2.0e-5 
+Tnom=25.0 
+version =3.3  hspver=98.2  paramchk=1 
....................... 
ends nmos_3p3 
....... 
.ENDL device_stat 
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