在线咨询
eetop公众号 创芯大讲堂 创芯人才网
切换到宽版

EETOP 创芯网论坛 (原名:电子顶级开发网)

手机号码,快捷登录

手机号码,快捷登录

找回密码

  登录   注册  

快捷导航
搜帖子
查看: 9047|回复: 12

[求助] 【已解决】hspice error:model name pmos_3p3 in the element 0:mm3

[复制链接]
发表于 2014-9-2 16:16:55 | 显示全部楼层 |阅读模式

马上注册,结交更多好友,享用更多功能,让你轻松玩转社区。

您需要 登录 才可以下载或查看,没有账号?注册

x
本帖最后由 dennisi123 于 2014-9-4 14:52 编辑

最近用hspice仿真,总是报错:

**error** model name pmos_3p3 in the element     0:mm4
is not defined.

**error** model name pmos_3p3 in the element     0:mm3
is not defined.

**error** model name nmos_3p3 in the element     0:mm2
is not defined.

**error** model name nmos_3p3 in the element     0:mm1
is not defined.
我用的spc文件摘录如下:
.subckt ad01d0 a b ci s co
Cg1_1 CI VSS  4.14168e-15
Cg1_2 B VSS  7.28435e-15
Cc2_2 B CI  2.32608e-16
Cg1_3 4 VSS  4.50593e-15
Cc1_3 4 CI  4.26413e-16
Cc3_3 4 B  5.17321e-16
Cg1_4 A VSS  5.35359e-15
Cc1_4 A B  8.94521e-16
Cc2_4 A 4  5.75607e-16
Cc3_4 A CI  6.62081e-16
Cg1_5 6 VSS  1.82215e-15
Cc1_5 6 4  2.89416e-16
Cc2_5 6 CI  3.60958e-16
Cc3_5 6 A  2.43636e-16
Cc5_5 6 B  4.41086e-16
Cg1_6 CO VSS  5.671e-16
Cc1_6 CO 4  1.55977e-16
Cc3_6 CO 6  6.05412e-18
Cg1_7 S VSS  5.4273e-16
Cc1_7 S 6  4.75992e-16
Cc2_7 S B  6.22657e-17
Cc3_7 S CO  1.81798e-16
Cc4_7 S 4  9.9208e-17
Cg1_8 12 VSS  2.24308e-16
Cc1_8 12 A  2.25903e-16
Cc2_8 12 CI  2.08555e-17
Cc3_8 12 4  6.34468e-17
Cc4_8 12 B  5.06795e-17
Cg1_9 11 VSS  1.09011e-16
Cc1_9 11 4  3.11922e-16
Cc2_9 11 CI  1.46254e-16
Cc3_9 11 6  2.14373e-17
Cc4_9 11 B  4.94114e-17
Cc5_9 11 A  3.28385e-17
Cg1_10 10 VSS  3.1507e-16
Cc1_10 10 CI  2.05234e-17
Cc2_10 10 4  6.54041e-17
Cc3_10 10 A  2.10968e-16
Cc4_10 10 B  4.95864e-17
Cc5_10 10 12  8.19885e-18
Cg1_11 9 VSS  4.55127e-16
Cc1_11 9 4  4.54445e-17
Cc2_11 9 CI  1.83156e-16
Cc3_11 9 A  8.9448e-17
Cc4_11 9 6  3.82871e-17
Cc5_11 9 11  2.55536e-17
Cc6_11 9 B  4.49332e-17
Cc1_12 18 4  1.53694e-17
Cc1_13 17 6  1.53694e-17
Cc1_14 16 6  2.45811e-17
Cc1_15 21 6  6.89651e-18
Cc2_15 21 4  1.77339e-17
Cc1_16 20 6  2.16748e-17
Cc2_16 20 4  1.77339e-17
Cc1_17 19 4  2.18841e-17
MM28 S 6 VDD VDD pmos_3p3 l=0.35u w=2.2u ad=1.975p pd=6.85u as=1.155p ps=3.25u
MM27 VDD 4 CO VDD pmos_3p3 l=0.35u w=2.2u ad=1.155p pd=3.25u as=1.795p ps=6.35u
MM23 19 A 4 VDD pmos_3p3 l=0.35u w=3.465u ad=1.1365p pd=4.1155u as=1.41827p
+ ps=4.33573u
MM18 19 B VDD VDD pmos_3p3 l=0.35u w=3.465u ad=1.1365p pd=4.1155u as=1.59572p
+ ps=4.52494u
MM26 11 4 6 VDD pmos_3p3 l=0.35u w=2.3u ad=1.2075p pd=3.35u as=1.25818p ps=3.62542u
MM24 20 CI 6 VDD pmos_3p3 l=0.35u w=3.6u ad=1.35p pd=4.35u as=1.96932p ps=5.67458u
MM21 21 A 20 VDD pmos_3p3 l=0.35u w=3.6u ad=1.35p pd=4.35u as=1.35p ps=4.35u
MM20 VDD B 21 VDD pmos_3p3 l=0.35u w=3.6u ad=3.4p pd=12.091u as=1.35p ps=4.35u
MM15 12 CI 4 VDD pmos_3p3 l=0.35u w=3.3u ad=1.7325p pd=4.35u as=1.35073p ps=4.12927u
MM22 VDD A 11 VDD pmos_3p3 l=0.35u w=3.4u ad=1.56578p pd=4.44006u as=1.43788p
+ ps=4.29512u
MM16 VDD CI 11 VDD pmos_3p3 l=0.35u w=3.627u ad=1.9593p pd=5.55463u as=1.53387p
+ ps=4.58188u
MM17 12 B VDD VDD pmos_3p3 l=0.35u w=3.3u ad=1.7325p pd=4.35u as=1.43606p ps=4.31632u
MM25 12 A VDD VDD pmos_3p3 l=0.35u w=3.194u ad=2.426p pd=7.844u as=1.38994p
+ ps=4.17768u
MM19 11 B VDD VDD pmos_3p3 l=0.35u w=2.3u ad=1.2075p pd=3.35u as=1.24245p ps=3.52237u
MM14 S 6 VSS VSS nmos_3p3 l=0.35u w=1.6u ad=1.57875p pd=5.262u as=0.84p ps=2.65u
MM13 VSS 4 CO VSS nmos_3p3 l=0.35u w=1.6u ad=0.84p pd=2.65u as=1.35p ps=5.15u
MM5 10 B VSS VSS nmos_3p3 l=0.35u w=2.394u ad=1.00768p pd=3.29613u as=0.989639p
+ ps=3.29613u
MM2 10 CI 4 VSS nmos_3p3 l=0.35u w=2.25u ad=0.947069p pd=3.09787u as=1.18125p ps=3.3u
MM12 9 4 6 VSS nmos_3p3 l=0.35u w=2u ad=1.05p pd=3.05u as=1.05p ps=3.05u
MM10 16 CI 6 VSS nmos_3p3 l=0.35u w=2u ad=0.65p pd=2.65u as=1.05p ps=3.05u
MM7 16 A 17 VSS nmos_3p3 l=0.35u w=2u ad=0.65p pd=2.65u as=0.65p ps=2.65u
MM6 VSS B 17 VSS nmos_3p3 l=0.35u w=2u ad=1.58p pd=5.832u as=0.65p ps=2.65u
MM1 9 CI VSS VSS nmos_3p3 l=0.35u w=2u ad=1.05p pd=3.05u as=1.06176p ps=3.10588u
MM11 10 A VSS VSS nmos_3p3 l=0.35u w=2.25u ad=2.19375p pd=6.45u as=0.930111p
+ ps=3.09787u
MM8 18 A 4 VSS nmos_3p3 l=0.35u w=2.25u ad=0.73125p pd=2.9u as=1.18125p ps=3.3u
MM4 VSS B 18 VSS nmos_3p3 l=0.35u w=2.25u ad=1.18125p pd=3.3u as=0.73125p ps=2.9u
MM9 9 A VSS VSS nmos_3p3 l=0.35u w=2.25u ad=1.18125p pd=3.3u as=1.19449p ps=3.49412u
MM3 9 B VSS VSS nmos_3p3 l=0.35u w=2.25u ad=1.18125p pd=3.3u as=1.18125p ps=3.3u
.ends
.subckt ad01d1 a b ci s co

大家有没有也遇到相同问题的?请问是怎么解决的?快流片了,着急 ,谢谢了!
发表于 2014-9-3 08:35:13 | 显示全部楼层
回复 1# dennisi123
    没model啊,人家不认识你写的nmos-3p3是啥子。或者是你调用的lib文件里面模型不叫这个名字
 楼主| 发表于 2014-9-3 09:42:07 | 显示全部楼层
回复 2# xi8meng

您好!我加了spice models了,是一个.hspice的文件,但是提示说已加密,需要解密,愁死我了
 楼主| 发表于 2014-9-4 14:32:22 | 显示全部楼层
本帖最后由 dennisi123 于 2014-9-4 14:52 编辑

感谢楼上的回答,是我的引用语法不对。引用spice models的时候应该这样写:.lib  "/home/LHG/zhangzy/0.35um_ANALOG_3.3V_5V_Salicide_459/spice_model/yi-046-sm005/attachement/sm046005-1j.hspice" typical  
其中typical是sm04600501j.hspice中定义的一个lib
 楼主| 发表于 2015-8-24 19:19:32 | 显示全部楼层
前几天更新了pdk,现在发现用新的hspice文件不能仿真了,报错:
model name pmos_3p3 in the element 0:mm8 is not defined
我引用的方式是:.lib './sm046005-15.hspice' typical,以前用是可以的,现在怎么不行了?
 楼主| 发表于 2015-8-24 19:21:40 | 显示全部楼层
sm046005-15.hspice文件截取如下:
.lib typical
.lib 'sm046005-15.hspice' rc
.lib 'sm046005-15.hspice' sigma
.lib 'sm046005-15.hspice' NT
.lib 'sm046005-15.hspice' PT
.lib 'sm046005-15.hspice' device
.endl typical
 楼主| 发表于 2015-8-24 19:24:24 | 显示全部楼层
.lib device
*-------------------------------------------------------------------------------------------------------
* 0.35um Logic Salicide Dual-gate Process with PLDD structure - Thin gate NMOS transistor without DNWell

.subckt nmos_3p3 d g s b w=0 l=0
+ as=0 ad=0 ps=0 pd=0 nrd=0 nrs=0 par=1 dtemp=0

m0 d g s b nmos_3p3 w=w l=l as=as ad=ad ps=ps pd=pd nrd=nrd nrs=nrs dtemp=dtemp
.model nmos_3p3 NMOS
+Level= 53
*+lmin=3.5e-7 lmax=1.0e-5 wmin=4.0e-7 wmax=2.0e-5
+Tnom=25.0
+version =3.3  hspver=98.2  paramchk=1
*+Tox= 7.69E-09
*+Toxm= 7.69E-09
+Tox= toxn_tn
+Toxm= toxn_tn
+Xj= xjn_tn
+xl= xln_tn
+xw= xwn_tn
+Nch= 2.0857000E+17
+lln= 1.0000000
,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,
.ends nmos_3p3
..........
...........
* 0.35um Logic Salicide Dual-gate Process with PLDD structure - Thin gate NMOS transistor without DNWell
.subckt nmos_3p3 d g s b w=0 l=0
+ as=0 ad=0 ps=0 pd=0 nrd=0 nrs=0 par=1 dtemp=0

+ par_vth_tnn=0.0121
+ par_k_tnn= 0.0136
+ par_l_tnn= 0
+ par_w_tnn= 0
+ par_leff_tnn = 'l - par_l_tnn'
+ par_weff_tnn = 'par*(w - par_w_tnn)'
+ p_sqrtarea_tnn = 'sqrt((par_leff_tnn)*(par_weff_tnn))'
+ var_k_tnn= '0.7071 * par_k_tnn* 1e-06 / p_sqrtarea_tnn'
+ var_vth_tnn='0.7071*par_vth_tnn* 1e-06 / p_sqrtarea_tnn'

+ mis_k_tnn = agauss (0, var_k_tnn, 1)
+ mis_vth_tnn = agauss (0, var_vth_tnn, 1)
+ std_u0n_tn='1-mis_k_tnn*sw_stat_mismatch'
+ mis_vthon_tn='mis_vth_tnn*sw_stat_mismatch'

m0 d g s b nmos_3p3 w=w l=l as=as ad=ad ps=ps pd=pd nrd=nrd nrs=nrs dtemp=dtemp

.model nmos_3p3 NMOS
+Level= 53
*+lmin=3.5e-7 lmax=1.0e-5 wmin=4.0e-7 wmax=2.0e-5
+Tnom=25.0
+version =3.3  hspver=98.2  paramchk=1
.......................
ends nmos_3p3
.......
.ENDL device_stat
***************************************************************************************************
*
发表于 2016-8-23 20:42:26 | 显示全部楼层
您好,我也遇到这个问题了,能把您的.sp文件的库包含那部分贴出来吗?谢谢!
发表于 2017-2-6 16:13:57 | 显示全部楼层
我也遇到了类似的问题,不过已经解决了,GF更新了工艺库,把MOS管变成了一个subckt,所以需要使用XMp1之类的表示mos管
发表于 2018-5-21 18:48:26 | 显示全部楼层
GOOD MATERIAL
您需要登录后才可以回帖 登录 | 注册

本版积分规则

关闭

站长推荐 上一条 /2 下一条


小黑屋| 手机版| 关于我们| 联系我们| 在线咨询| 隐私声明| EETOP 创芯网
( 京ICP备:10050787号 京公网安备:11010502037710 )

GMT+8, 2024-12-22 15:54 , Processed in 0.028143 second(s), 8 queries , Gzip On, Redis On.

eetop公众号 创芯大讲堂 创芯人才网
快速回复 返回顶部 返回列表