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本帖最后由 ICSYS 于 2014-8-12 20:17 编辑
CELL COMPARISON RESULTS
# # #####################
# # # #
# # INCORRECT #
# # # #
# # #####################
Error: Different numbers of nets (see below).
Error: Connectivity errors.
Warning: Extra ports in layout.
LAYOUT CELL NAME: AN2D1BWP12THVT
SOURCE CELL NAME: AN2D1BWP12THVT
--------------------------------------------------------------------------------------------------------------
INITIAL NUMBERS OF OBJECTS
--------------------------
Layout Source Component Type
------ ------ --------------
Ports: 7 5 *
Nets: 9 7 *
Instances: 3 3 MN (4 pins)
3 3 MP (4 pins)
------ ------
Total Inst: 6 6
NUMBERS OF OBJECTS AFTER TRANSFORMATION
---------------------------------------
Layout Source Component Type
------ ------ --------------
Ports: 7 5 *
Nets: 8 6 *
Instances: 1 1 _invv (4 pins)
1 1 _nand2v (5 pins)
------ ------
Total Inst: 2 2
* = Number of objects in layout different from number in source.
**************************************************************************************************************
INCORRECT OBJECTS
**************************************************************************************************************
LEGEND:
-------
ne = Naming Error (same layout name found in source
circuit, but object was matched otherwise).
**************************************************************************************************************
INCORRECT NETS
DISC# LAYOUT NAME SOURCE NAME
**************************************************************************************************************
1 Net 9 ** no similar net **
--------------------------------------------------------------------------------------------------------------
2 Net 10 ** no similar net **
**************************************************************************************************************
INCORRECT INSTANCES
DISC# LAYOUT NAME SOURCE NAME
**************************************************************************************************************
3 M5(0.620,0.880) MP(PCH_HVT) M_u3-M_u3 MP(PCH_HVT)
g: 12 g: net6
s: Z s: Z
d: VDD d: VDD
b: 10 ** no similar net **
** VDD ** b: VDD
--------------------------------------------------------------------------------------------------------------
4 M2(0.620,0.180) MN(NCH_HVT) M_u3-M_u2 MN(NCH_HVT)
g: 12 g: net6
s: Z s: Z
d: VSS d: VSS
b: 9 ** no similar net **
** VSS ** b: VSS
--------------------------------------------------------------------------------------------------------------
5 M1(0.380,0.180) MN(NCH_HVT) M_u2-M_u4 MN(NCH_HVT)
g: A2 g: A2
d: 12 ** net6 **
b: 9 ** no similar net **
** VSS ** d: VSS
** VSS ** b: VSS
--------------------------------------------------------------------------------------------------------------
6 M0(0.180,0.180) MN(NCH_HVT) M_u2-M_u3 MN(NCH_HVT)
g: A1 g: A1
d: VSS b: VSS
b: 9 ** no similar net **
** 12 ** d: net6
--------------------------------------------------------------------------------------------------------------
7 M4(0.380,1.190) MP(PCH_HVT) M_u2-M_u2 MP(PCH_HVT)
g: A2 g: A2
s: 12 s: net6
d: VDD d: VDD
b: 10 ** no similar net **
** VDD ** b: VDD
--------------------------------------------------------------------------------------------------------------
8 M3(0.180,1.190) MP(PCH_HVT) M_u2-M_u1 MP(PCH_HVT)
g: A1 g: A1
s: 12 s: net6
d: VDD d: VDD
b: 10 ** no similar net **
** VDD ** b: VDD
**************************************************************************************************************
INFORMATION AND WARNINGS
**************************************************************************************************************
Matched Matched Unmatched Unmatched Component
Layout Source Layout Source Type
------- ------- --------- --------- ---------
Ports: 5 5 2 0
Nets: 6 6 2 0
Instances: 1 1 0 0 _invv
1 1 0 0 _nand2v
------- ------- --------- ---------
Total Inst: 2 2 0 0
o Extra Ports in Layout:
9 10
o Initial Correspondence Points:
Ports: VDD VSS Z A1 A2
CELL COMPARISON RESULTS
# # #####################
# # # #
# # INCORRECT #
# # # #
# # #####################
Error: Different numbers of nets (see below).
Error: Connectivity errors.
Warning: Extra ports in layout.
LAYOUT CELL NAME: AN3XD1BWP12THVT
SOURCE CELL NAME: AN3XD1BWP12THVT
--------------------------------------------------------------------------------------------------------------
INITIAL NUMBERS OF OBJECTS
--------------------------
Layout Source Component Type
------ ------ --------------
Ports: 8 6 *
Nets: 11 9 *
Instances: 4 4 MN (4 pins)
4 4 MP (4 pins)
------ ------
Total Inst: 8 8
NUMBERS OF OBJECTS AFTER TRANSFORMATION
---------------------------------------
Layout Source Component Type
------ ------ --------------
Ports: 8 6 *
Nets: 9 7 *
Instances: 1 1 _invv (4 pins)
1 1 _nand3v (6 pins)
------ ------
Total Inst: 2 2
* = Number of objects in layout different from number in source.
**************************************************************************************************************
INCORRECT OBJECTS
**************************************************************************************************************
LEGEND:
-------
ne = Naming Error (same layout name found in source
circuit, but object was matched otherwise).
**************************************************************************************************************
INCORRECT NETS
DISC# LAYOUT NAME SOURCE NAME
**************************************************************************************************************
1 Net 10 ** no similar net **
--------------------------------------------------------------------------------------------------------------
2 Net 11 ** no similar net **
**************************************************************************************************************
INCORRECT INSTANCES
DISC# LAYOUT NAME SOURCE NAME
**************************************************************************************************************
3 M7(0.760,0.880) MP(PCH_HVT) M_u3-M_u3 MP(PCH_HVT)
g: 13 g: net7
s: Z s: Z
d: VDD d: VDD
b: 11 ** no similar net **
** VDD ** b: VDD
--------------------------------------------------------------------------------------------------------------
4 M3(0.760,0.180) MN(NCH_HVT) M_u3-M_u2 MN(NCH_HVT)
g: 13 g: net7
s: Z s: Z
d: VSS d: VSS
b: 10 ** no similar net **
** VSS ** b: VSS
--------------------------------------------------------------------------------------------------------------
5 M2(0.520,0.180) MN(NCH_HVT) M_u4-M_u6 MN(NCH_HVT)
g: A3 g: A3
d: 13 ** net7 **
b: 10 ** no similar net **
** VSS ** d: VSS
** VSS ** b: VSS
--------------------------------------------------------------------------------------------------------------
6 M0(0.160,0.180) MN(NCH_HVT) M_u4-M_u4 MN(NCH_HVT)
g: A1 g: A1
d: VSS b: VSS
b: 10 ** no similar net **
--------------------------------------------------------------------------------------------------------------
7 M1(0.340,0.180) MN(NCH_HVT) M_u4-M_u5 MN(NCH_HVT)
g: A2 g: A2
b: 10 ** no similar net **
** 13 ** d: net7
** VSS ** b: VSS
--------------------------------------------------------------------------------------------------------------
8 M6(0.520,1.070) MP(PCH_HVT) M_u4-M_u3 MP(PCH_HVT)
g: A3 g: A3
s: 13 s: net7
d: VDD d: VDD
b: 11 ** no similar net **
** VDD ** b: VDD
--------------------------------------------------------------------------------------------------------------
9 M4(0.160,1.070) MP(PCH_HVT) M_u4-M_u1 MP(PCH_HVT)
g: A1 g: A1
s: 13 s: net7
d: VDD d: VDD
b: 11 ** no similar net **
** VDD ** b: VDD
--------------------------------------------------------------------------------------------------------------
10 M5(0.340,1.070) MP(PCH_HVT) M_u4-M_u2 MP(PCH_HVT)
g: A2 g: A2
s: 13 s: net7
d: VDD d: VDD
b: 11 ** no similar net **
** VDD ** b: VDD
**************************************************************************************************************
INFORMATION AND WARNINGS
**************************************************************************************************************
Matched Matched Unmatched Unmatched Component
Layout Source Layout Source Type
------- ------- --------- --------- ---------
Ports: 6 6 2 0
Nets: 7 7 2 0
Instances: 1 1 0 0 _invv
1 1 0 0 _nand3v
------- ------- --------- ---------
Total Inst: 2 2 0 0
o Extra Ports in Layout:
10 11
o Initial Correspondence Points:
Ports: VDD VSS Z A1 A2 A3
CELL COMPARISON RESULTS
# # #####################
# # # #
# # INCORRECT #
# # # #
# # #####################
Error: Different numbers of nets (see below).
Error: Connectivity errors.
Warning: Extra ports in layout.
LAYOUT CELL NAME: AO21D1BWP12THVT
SOURCE CELL NAME: AO21D1BWP12THVT
--------------------------------------------------------------------------------------------------------------
INITIAL NUMBERS OF OBJECTS
--------------------------
Layout Source Component Type
------ ------ --------------
Ports: 8 6 *
Nets: 11 9 *
Instances: 4 4 MN (4 pins)
4 4 MP (4 pins)
------ ------
Total Inst: 8 8
NUMBERS OF OBJECTS AFTER TRANSFORMATION
---------------------------------------
Layout Source Component Type
------ ------ --------------
Ports: 8 6 *
Nets: 9 7 *
Instances: 1 1 MN (4 pins)
1 1 SPUP_2_1 (4 pins)
1 1 _invv (4 pins)
1 1 _smn2v (4 pins)
------ ------
Total Inst: 4 4
* = Number of objects in layout different from number in source.
**************************************************************************************************************
INCORRECT OBJECTS
**************************************************************************************************************
LEGEND:
-------
ne = Naming Error (same layout name found in source
circuit, but object was matched otherwise).
**************************************************************************************************************
INCORRECT NETS
DISC# LAYOUT NAME SOURCE NAME
**************************************************************************************************************
1 Net VSS VSS
10
--------------------------------------------------------------------------------------------------------------
2 Net 11 ** missing net **
**************************************************************************************************************
INCORRECT INSTANCES
DISC# LAYOUT NAME SOURCE NAME
**************************************************************************************************************
3 M7(0.780,0.880) MP(PCH_HVT) MI8-M_u3 MP(PCH_HVT)
g: 14 g: net59
s: Z s: Z
d: VDD d: VDD
b: 11 ** missing net **
** VDD ** b: VDD
--------------------------------------------------------------------------------------------------------------
4 M4(0.160,0.880) MP(PCH_HVT) M_u4 MP(PCH_HVT)
g: A2 g: A2
b: 11 ** missing net **
** VDD ** b: VDD
--------------------------------------------------------------------------------------------------------------
5 M5(0.340,0.880) MP(PCH_HVT) M_u3 MP(PCH_HVT)
g: A1 g: A1
b: 11 ** missing net **
** VDD ** b: VDD
--------------------------------------------------------------------------------------------------------------
6 M6(0.540,0.880) MP(PCH_HVT) M_u2 MP(PCH_HVT)
g: B g: B
b: 11 ** missing net **
** VDD ** b: VDD
**************************************************************************************************************
INFORMATION AND WARNINGS
**************************************************************************************************************
Matched Matched Unmatched Unmatched Component
Layout Source Layout Source Type
------- ------- --------- --------- ---------
Ports: 7 6 1 0
Nets: 8 7 1 0
Instances: 1 1 0 0 MN(NCH_HVT)
1 1 0 0 SPUP_2_1
1 1 0 0 _invv
1 1 0 0 _smn2v
------- ------- --------- ---------
Total Inst: 4 4 0 0
o Extra Ports in Layout:
11
o Initial Correspondence Points:
Ports: VDD VSS Z A2 A1 B |
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发表于 2014-8-12 14:38:33
发表于 2014-8-12 14:57:52
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