我是FPGA初学者,在仿真课本上一个例子,功能仿真时报错:Error: Zero-time oscillation in node "|mult_for|outcome~88" at time 0.0 ns. Check the design or vector source file for combinational loop.搞不明白是什么原因,希望大家能够帮忙,再此十分感谢。程序veriloghdl代码如下(两个8位数相乘):
module mult_for(outcome,a,b);
parameter SIZE=8;
input[SIZE:1] a,b;
output reg[2*SIZE:1] outcome;
reg [2*SIZE:1] temp_a;
integer i;
always @(a,b)
begin outcome<=0; temp_a=a;
for(i=1;i<=SIZE;i=i+1)
if( b[i]) outcome<=outcome+(temp_a<<(i-1));
end
endmodule