[PLL系列丛书之九]Phase-Locked Loop Circuit Design by Dan H. Wolaver

mxh7408 · 发表于 2013-7-24 18:03:21

太零碎了

yxy7968 · 发表于 2013-7-24 21:40:33

能够解压，但希望以后这样的文档不用分开压，显得不够厚道。

sathya · 发表于 2013-11-13 10:43:37

A phase detector output of +1 makes the divide-by-M circuit count up. A phase
detector output of -1 makes the divide-by-M circuit count down. Therefore, the
output frequency from the divide-by-M counter has an average value described by
(9.72):
Df = uFM /M (9.72)
Equation (9.73) gives the gain of the VCO block by substituting (9.72) into (9.70)
and taking the derivative:
Kv = dfout /du = FM /(2MN) (9.73)
Figure 9.72 shows a block diagram using these constants. The l/s block converts
frequency to phase. Figure 9.72 models a first-order loop. Equation (9.74) computes
the unity-gain bandwidth from multiplying the blocks in the figure:
vx = K = [2FM /(MN)] rad/cycle