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发表于 2014-7-16 15:24:39
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回复 10# sea11038
bosoho@ubuntu:~$ lmli
bosoho@ubuntu:~$ 0:26:53 (lmgrd) -----------------------------------------------
0:26:53 (lmgrd) Please Note:
0:26:53 (lmgrd)
0:26:53 (lmgrd) This log is intended for debug purposes only.
0:26:53 (lmgrd) In order to capture accurate license
0:26:53 (lmgrd) usage data into an organized repository,
0:26:53 (lmgrd) please enable report logging. Use Macrovision's
0:26:53 (lmgrd) software license administration solution,
0:26:53 (lmgrd) FLEXnet Manager, to readily gain visibility
0:26:53 (lmgrd) into license usage data and to create
0:26:53 (lmgrd) insightful reports on critical information like
0:26:53 (lmgrd) license availability and usage. FLEXnet Manager
0:26:53 (lmgrd) can be fully automated to run these reports on
0:26:53 (lmgrd) schedule and can be used to track license
0:26:53 (lmgrd) servers and usage across a heterogeneous
0:26:53 (lmgrd) network of servers including Windows NT, Linux
0:26:53 (lmgrd) and UNIX. Contact Macrovision at
0:26:53 (lmgrd) www.macrovision.com for more details on how to
0:26:53 (lmgrd) obtain an evaluation copy of FLEXnet Manager
0:26:53 (lmgrd) for your enterprise.
0:26:53 (lmgrd)
0:26:53 (lmgrd) -----------------------------------------------
0:26:53 (lmgrd)
0:26:53 (lmgrd)
0:26:53 (lmgrd) FLEXnet Licensing (v10.8.2.1 build 30341) started on ubuntu (linux) (7/16/2014)
0:26:53 (lmgrd) Copyright (c) 1988-2006 Macrovision Europe Ltd. and/or Macrovision Corporation. All Rights Reserved.
0:26:53 (lmgrd) US Patents 5,390,297 and 5,671,412.
0:26:53 (lmgrd) World Wide Web: http://www.macrovision.com
0:26:53 (lmgrd) License file(s): /home/eda/ic610/share/license/license.dat
0:26:53 (lmgrd) lmgrd tcp-port 5280
0:26:53 (lmgrd) Starting vendor daemons ...
0:26:53 (lmgrd) Started cdslmd (internet tcp_port 54325 pid 2718)
0:26:53 (cdslmd) FLEXnet Licensing version v10.8.2.1 build 30341
0:26:53 (cdslmd) Invalid license key (inconsistent authentication code)
0:26:53 (cdslmd) ==>FEATURE Cadence_3D_Design_Viewer cdslmd 16.0 31-dec-2025 uncounted \
01357D06E4AD VENDOR_STRING=Team_EFA_2006 HOSTID=ANY ck=78 \
SIGN2="0D0D EA79 E0C1 4F48 4DCF 770A E1AE F9EF 70FB FF11 B46D \
CB35 F1D2 9A45 F4A3 05E1 EB0A CEF4 8396 87BA 7B4A BA27 CED9 \
F214 BED4 2DC6 BF6A F385 8BDA C611"
0:26:53 (cdslmd) Invalid license key (inconsistent authentication code)
0:26:53 (cdslmd) ==>FEATURE Capture cdslmd 16.0 31-dec-2025 uncounted FC5BE9761A8C \
VENDOR_STRING=Team_EFA_2006 HOSTID=ANY ck=115 SIGN2="172D DEBE \
A0EB 398F CC4A 6F83 94C4 9562 ED81 D592 F833 18A4 F5A7 009E \
EBE4 0F57 1D31 3017 21F4 CE68 9C92 4062 39AF 69FA 9B04 DEA3 \
F3BB 5CF1 2709 1BDA"
0:26:53 (cdslmd) Server started on ubuntu for: LayoutPlus
0:26:53 (cdslmd) Allegro_Librarian Allegro_Viewer_Plus PspiceAD
0:26:53 (cdslmd) PspiceAA Allegro_studio ConceptHDL
0:26:53 (cdslmd) PCB_librarian_expert SiP_Digital_Architect_GXL SiP_Digital_Architect_L
0:26:53 (cdslmd) SiP_Digital_Architect_XL SiP_Digital_Layout_GXL SiP_Digital_SI_XL
0:26:53 (cdslmd) SiP_RF_Architect_L SiP_RF_Architect_XL SiP_RF_Layout_GXL
0:26:53 (cdslmd) Allegro_Design_Editor_620 Allegro_PCB_SI_230 Allegro_PCB_SI_630
0:26:53 (cdslmd) SPECCTRAQuest_EE PCB_designer CHDL_DesignAccess
0:26:53 (cdslmd) PE_Librarian Checkplus_Expert Concept_HDL_rules_checker
0:26:53 (cdslmd) Concept_HDL_studio PCB_design_studio adv_package_designer_expert
0:26:53 (cdslmd) PCB_studio_variants PCB_design_expert adv_package_engineer_expert
0:26:53 (cdslmd) SPECCTRAQuest_SI_expert Concept_HDL_expert Allegro_design_expert
0:26:53 (cdslmd) advanced_package_designer Allegro_designer_suite OrCAD_PCB_Router
0:26:53 (cdslmd) OrCAD_PCB_Designer_PSpice OrCAD_PCB_Designer UNISON_SPECCTRA_6U
0:26:53 (cdslmd) SPECCTRA_Unison_Ultra SPECCTRA_Unison_PCB Unison_SPECCTRA_4U
0:26:53 (cdslmd) Allegro_PCB_Design_620 Allegro_Package_SI_620_Suite Allegro_PCB_SI_620
0:26:53 (cdslmd) Allegro_Pkg_Designer_620_Suite Allegro_PCB_Router_230 Allegro_PCB_Design_230
0:26:53 (cdslmd) Allegro_PCB_SI_630_Suite Allegro_PCB_Router_210 Allegro_PCB_Router_610
0:26:53 (cdslmd) SPECCTRA_VT SPECCTRA_QE SPECCTRA_performance
0:26:53 (cdslmd) SPECCTRA_PCB SPECCTRA_HP SPECCTRA_expert_system
0:26:53 (cdslmd) SPECCTRA_expert SPECCTRA_DFM SPECCTRA_autoroute
0:26:53 (cdslmd) SPECCTRA_APD SPECCTRA_ADV SPECCTRA_6U
0:26:53 (cdslmd) SPECCTRA_256U Allegro_performance Allegro_PCB_RF
0:26:53 (cdslmd) Allegro_PCB_Partitioning Advanced_Pkg_Engineer_3D PowerIntegrity
0:26:53 (cdslmd) SPECCTRAQuest 111 12141
0:26:53 (cdslmd) 14000 14010 14020
0:26:53 (cdslmd) 14040 14060 206
0:26:53 (cdslmd) 207 21060 21400
0:26:53 (cdslmd) 276 283 300
0:26:53 (cdslmd) 3000 3001 3011
0:26:53 (cdslmd) 302 305 311
0:26:53 (cdslmd) 3111 32100 32101
0:26:53 (cdslmd) 32120 32125 32130
0:26:53 (cdslmd) 32140 32150 32500
0:26:53 (cdslmd) 32501 32505 32510
0:26:53 (cdslmd) 32520 32521 32530
0:26:53 (cdslmd) 32760 33015 33016
0:26:53 (cdslmd) 33301 33500 33580
0:26:53 (cdslmd) 34500 34510 34511
0:26:53 (cdslmd) 34530 34570 34580
0:26:53 (cdslmd) 365 370 37100
0:26:53 (cdslmd) 374 38500 38520
0:26:53 (cdslmd) 4000 501 5100
0:26:53 (cdslmd) 550 570 681
0:26:53 (cdslmd) 70000 70110 70120
0:26:53 (cdslmd) 70130 70510 70520
0:26:53 (cdslmd) 71110 71120 71130
0:26:53 (cdslmd) 71510 71520 73510
0:26:53 (cdslmd) 73520 900 90001
0:26:53 (cdslmd) 940 945 95100
0:26:53 (cdslmd) 95115 95120 952
0:26:53 (cdslmd) 95200 95210 95220
0:26:53 (cdslmd) 95255 95300 95310
0:26:53 (cdslmd) 95320 95400 972
0:26:53 (cdslmd) 974 plotVersa LEAPFROG-CV
0:26:53 (cdslmd) _21900 Datapath_Preview_Option Virtuoso_Turbo
0:26:53 (cdslmd) Virtuoso_XL Encounter_C Virtuoso_Digital_Implement
0:26:53 (cdslmd) Virtuoso_XL_Basic Virtuoso_Schem_Option Virtuoso_Turbo_Basic
0:26:53 (cdslmd) OASIS_Simulation_Interface OASIS_RFDE Artist_Optimizer
0:26:53 (cdslmd) Artist_Statistics Corners_Analysis Affirma_3rdParty_Sim_Interface
0:26:53 (cdslmd) Affirma_RF_IC_package_modeler SpectreRF Substrate_Coupling_Analysis
0:26:53 (cdslmd) Affirma_RF_SPW_model_link Virtuoso_Core_Optimizer Virtuoso_Core_Characterizer
0:26:53 (cdslmd) ULTRASIM RELXPERT UET
0:26:53 (cdslmd) Affirma_AMS_distrib_processing ADE_VoltageStorm_Option ADE_ElectronStorm_Option
0:26:53 (cdslmd) LAS_Cell_Optimization Virtuoso_Spectre Virtuoso_Spectre_RF
0:26:53 (cdslmd) virtuoso_chip_editor Virtuoso_Layout_Migrate ConcICe_Option
0:26:53 (cdslmd) AMS_environment DRAC2CORE DRAC3CORE
0:26:53 (cdslmd) DRAC3DRC DRACDIST DRACERC
0:26:53 (cdslmd) Distributed_Dracula_Option DRAC3LVS DRACLPE
0:26:53 (cdslmd) DRACPRE DRACLVS Assura_RCX-PL
0:26:53 (cdslmd) Assura_RCX-FS Assura_RCX-MP Assura_RCX-HF
0:26:53 (cdslmd) Assura_DRC Assura_LVS Assura_MP
0:26:53 (cdslmd) Assura_OPC Assura_RCX Assura_SI-TL
0:26:53 (cdslmd) Assura_SI Assura_SiMC Assura_SiVL
0:26:53 (cdslmd) Assura_UI Assura_DV_design_rule_checker Assura_DV_parasitic_extractor
0:26:53 (cdslmd) Assura_DV_LVS_checker Physical_Verification_Sys_L Physical_Verification_Sys_XL
0:26:53 (cdslmd) skillDev Affirma_sim_analysis_env Virtuoso_Multi_mode_Simulation
0:26:53 (cdslmd) Virtuoso_Schematic_Editor_L Virtuoso_Schematic_Editor_XL Virtuoso_Schematic_Editor_GXL
0:26:53 (cdslmd) Composer_EDIF300_Connectivity Analog_Design_Environment_L Analog_Design_Environment_XL
0:26:53 (cdslmd) Analog_Design_Environment_GXL Virtuoso_Visual_Analysis_XL Composer_EDIF300_Schematic
0:26:53 (cdslmd) Virtuoso_Layout_Suite_L Virtuoso_Layout_Suite_XL Virtuoso_Layout_Suite_GXL
0:26:53 (cdslmd) Virtuoso_Constraint_API Spectre_BTAHVMOS_Models Spectre_BTASOI_Models
0:26:53 (cdslmd) tw01 tw02
0:26:53 (cdslmd)
0:26:53 (cdslmd) All FEATURE lines for cdslmd behave like INCREMENT lines
0:26:53 (cdslmd)
0:26:53 (lmgrd) cdslmd using TCP-port 54325
bosoho@ubuntu:~$ icfb
0:27:29 (cdslmd) TCP_NODELAY NOT enabled
0:27:42 (cdslmd) OUT: "Virtuoso_Schematic_Editor_L" bosoho@ubuntu
0:27:42 (cdslmd) IN: "Virtuoso_Schematic_Editor_L" bosoho@ubuntu
0:27:42 (cdslmd) OUT: "Virtuoso_Schematic_Editor_XL" bosoho@ubuntu
0:27:42 (cdslmd) IN: "Virtuoso_Schematic_Editor_XL" bosoho@ubuntu |
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发表于 2014-7-16 19:59:51
发表于 2014-7-17 09:28:42
