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本帖最后由 abcn101 于 2014-7-8 09:51 编辑
这是一个CLOCK GATING HOLD 违例，时间也不是很大，0.4ns左右。
按理说工具可以简单的加一个DELAY CELL或者若干INV就可以解决了，但为啥它就不修呢？
我已经反复地执行optDesign -hold了，没用。
- Path 1: VIOLATED Clock Gating Hold Check with Pin u217/B
- Endpoint: u217/AN (v) checked with trailing edge of 'SYS_CLK'
- Beginpoint: cpu_clk_gate_reg/Q (v) triggered by trailing edge of 'SYS_CLK'
- Path Groups: {clkgate}
- Other End Arrival Time 20.039
- + Clock Gating Hold 0.200
- + Phase Shift 0.000
- + Uncertainty 0.300
- = Required Time 20.539
- Arrival Time 20.141
- Slack Time -0.398
- Clock Fall Edge 20.000
- = Beginpoint Arrival Time 20.000
- Timing Path:
- +----------------------------------------------------------------------------------+
- | Instance | Arc | Cell | Slew | Delay | Arrival | Required |
- | | | | | | Time | Time |
- |------------------+-------------+------------+-------+-------+---------+----------|
- | clksw3_m | clk_out v | clksw3 | | | 20.000 | 20.398 |
- | cpu_clk_gate_reg | GN v -> Q v | LATNHD1X | 0.046 | 0.141 | 20.141 | 20.539 |
- | u217 | AN v | NOR2B1HD1X | 0.046 | 0.000 | 20.141 | 20.539 |
- +----------------------------------------------------------------------------------+
- Clock Fall Edge 20.000
- = Beginpoint Arrival Time 20.000
- Other End Path:
- +-------------------------------------------------------------------------+
- | Instance | Arc | Cell | Slew | Delay | Arrival | Required |
- | | | | | | Time | Time |
- |----------+------------+------------+-------+-------+---------+----------|
- | clksw3_m | clk_out v | clksw3 | | | 20.000 | 19.602 |
- | u216 | A v -> Z ^ | INVHDPX | 0.061 | 0.039 | 20.039 | 19.641 |
- | u217 | B ^ | NOR2B1HD1X | 0.061 | 0.000 | 20.039 | 19.641 |
- +-------------------------------------------------------------------------+
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发表于 2014-7-8 09:20:08
发表于 2014-7-8 22:02:32
