各位大侠: 我在采用quartus 2 12.1版本进行设计时,调用提拱的FIR COMPILER 2生成的IP核,而后进行Modelsim进行RTL仿真,出现以下错误信息:
# ** Error: (vlog-7) Failed to open design unit file "D:……hf.vo" in read mode.
#
# No such file or directory. (errno = ENOENT)
# ** Error: C:/altera/modelsim/modelsim_ase/win32aloem/vlog failed.