Verilog程序运行时序错乱了

sgg19964 · 发表于 2014-6-5 10:56:04

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这是我写的一段计算电机转速的程序，电机不通电时可以正常运行，电机通电后运行时序不正常了。这是用chipscope截的信号图，正常应该是在pulse的上升沿计数器加一才对。
下面是我的源程序，望大神们帮我看下代码有没有问题，
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: BUAA
// Engineer:
//
// Create Date: 16:26:01 05/22/2014
// Design Name:
// Module Name: Xintf
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module Xintf(
clki,
addr,
data,
READY,
XZC0,
XZC6,
XZC7,
XRDn,
XRnW,
dspCLKOUT,
halla_i,
hallb_i,
hallc_i,
pulse,
clk_D,
devide,
pwm_in,
pwm_out,
int_DSP
//int
//speed

);
input  halla_i;
input  hallb_i;
input  hallc_i;
input clki;
input [19:0] addr;
input XZC0;
input XZC6;
input XZC7;
input XRDn;
input XRnW;
input DSPCLKOUT;
input [11:0] pwm_in;
output [11:0] pwm_out;
output reg int_DSP;//DSP外部中断
output reg [15:0] data;
output wire READY;
output reg pulse;
output wire clk_D;

reg [15:0] speed;
reg [46:0] timer;
reg [15:0] pulse_counter[9:0];
//reg [15:0] speed;
reg [9:0] int;
reg [9:0]int_clear;
output reg devide;
reg [20:0] counter;
wire en;

wire CLK0,CLKFB;
wire  CLKDV;
DCM #(
   .CLKDV_DIVIDE(10), // Divide by: 1.5,2.0,2.5,3.0,3.5,4.0,4.5,5.0,5.5,6.0,6.5
                        // 7.0,7.5,8.0,9.0,10.0,11.0,12.0,13.0,14.0,15.0 or 16.0
   .CLKFX_DIVIDE(1), // Can be any integer from 1 to 32
   .CLKFX_MULTIPLY(4), // Can be any integer from 2 to 32
   .CLKIN_DIVIDE_BY_2("FALSE"), // TRUE/FALSE to enable CLKIN divide by two feature
   .CLKIN_PERIOD(10.0), // Specify period of input clock in ns from 1.25 to 1000.00
   .CLKOUT_PHASE_SHIFT("NONE"), // Specify phase shift mode of NONE or FIXED
   .CLK_FEEDBACK("1X"), // Specify clock feedback of NONE or 1X
//    .DCM_PERFORMANCE_MODE("MAX_SPEED"), // Can be MAX_SPEED or MAX_RANGE
   .DESKEW_ADJUST("SYSTEM_SYNCHRONOUS"), // SOURCE_SYNCHRONOUS, SYSTEM_SYNCHRONOUS or
                                          // an integer from 0 to 15
   .DFS_FREQUENCY_MODE("LOW"), // LOW or HIGH frequency mode for frequency synthesis
   .DLL_FREQUENCY_MODE("LOW"), // LOW, HIGH, or HIGH_SER frequency mode for DLL
   .DUTY_CYCLE_CORRECTION("TRUE"), // Duty cycle correction, TRUE or FALSE
   .FACTORY_JF(16'hf0f0), // FACTORY JF value suggested to be set to 16'hf0f0
   .PHASE_SHIFT(0), // Amount of fixed phase shift from -255 to 1023
   .STARTUP_WAIT("FALSE") // Delay configuration DONE until DCM LOCK, TRUE/FALSE
) DCM_BASE_inst (
   .CLK0(CLK0),       // 0 degree DCM CLK output
   .CLK180(),    // 180 degree DCM CLK output
   .CLK270(),    // 270 degree DCM CLK output
   .CLK2X(),    // 2X DCM CLK output
   .CLK2X180(), // 2X, 180 degree DCM CLK out
   .CLK90(),    // 90 degree DCM CLK output
   .CLKDV(CLKDV),    // Divided DCM CLK out (CLKDV_DIVIDE)
   .CLKFX(),    // DCM CLK synthesis out (M/D)
   .CLKFX180(), // 180 degree CLK synthesis out
   .LOCKED(),    // DCM LOCK status output
   .CLKFB(CLKFB),    // DCM clock feedback
   .CLKIN(clki),    // Clock input (from IBUFG, BUFG or DCM)
   .RST(0)          // DCM asynchronous reset input
);

  BUFG BUFG_inst1 (
   .O(CLKFB),    // Clock buffer output
   .I(CLK0)    // Clock buffer input
);
BUFG BUFG_inst2 (
   .O(clk_D),    // Clock buffer output，50M colck
   .I(CLKDV)    // Clock buffer input
);

always @(posedge clk_D)
begin
timer <= timer+1;
if(timer == 3000000)//0.1S
begin
  timer <= 1;
  int[0] <= 1;
end
/* else if(timer == 300000)
begin
  int[1] <= 1;
end
else if(timer == 600000)
begin
  int[2] <= 1;
end
else if(timer == 900000)
begin
  int[3] <= 1;
end
else if(timer == 1200000)
begin
  int[4] <= 1;
end
else if(timer == 1500000)
begin
  int[5] <= 1;
end
else if(timer == 1800000)
begin
  int[6] <= 1;
end
else if(timer == 2100000)
begin
  int[7] <= 1;
end
else if(timer == 2400000)
begin
  int[8] <= 1;
end
else if(timer == 2700000)
begin
  int[9] <= 1;
end
*/
else
  int <= int & (~int_clear);
//else if(int_clear[0] == 1)
//begin
// int[0] <= 0;
//end

end
always @(posedge clk_D)
begin
counter <= counter + 1;
if(counter == 15000)
begin
  counter <= 0;
  devide <= ~devide;
end
end

always @(posedge pulse)
begin
if(int[0] == 0)
begin
  pulse_counter[0] <= pulse_counter[0] + 1;
  int_clear[0] <= 0;
end
else if(int[0] == 1)
begin
  speed <= pulse_counter[0];
  pulse_counter[0] <= 1;
  int_clear[0] <= 1;
end
/*
if(int[1] == 0)
begin
  pulse_counter[1] <= pulse_counter[1] + 1;
  int_clear[1] <= 0;
end
else if(int[1] == 1 && !int[0])
begin
  speed <= pulse_counter[1];
  pulse_counter[1] <= 1;
  int_clear[1] <= 1;
end

if(int[2] == 0)
begin
  pulse_counter[2] <= pulse_counter[2] + 1;
  int_clear[2] <= 0;
end
else if(int[2] == 1 && !(int[0]|int[1]))
begin
  speed <= pulse_counter[2];
  pulse_counter[2] <= 1;
  int_clear[2] <= 1;
end

if(int[3] == 0)
begin
  pulse_counter[3] <= pulse_counter[3] + 1;
  int_clear[3] <= 0;
end
else if(int[3] == 1 && !(int[0]|int[1]|int[2]))
begin
  speed <= pulse_counter[3];
  pulse_counter[3] <= 1;
  int_clear[3] <= 1;
end

if(int[4] == 0)
begin
  pulse_counter[4] <= pulse_counter[4] + 1;
  int_clear[4] <= 0;
end
else if(int[4] == 1 && !(int[0]|int[1]|int[2]|int[3]))
begin
  speed <= pulse_counter[4];
  pulse_counter[4] <= 1;
  int_clear[4] <= 1;
end

if(int[5] == 0)
begin
  pulse_counter[5] <= pulse_counter[5] + 1;
  int_clear[5] <= 0;
end
else if(int[5] == 1 && !(int[0]|int[1]|int[2]|int[3]|int[4]))
begin
  speed <= pulse_counter[5];
  pulse_counter[5] <= 1;
  int_clear[5] <= 1;
end

if(int[6] == 0)
begin
  pulse_counter[6] <= pulse_counter[6] + 1;
  int_clear[6] <= 0;
end
else if(int[6] == 1 && !(int[0]|int[1]|int[2]|int[3]|int[4]|int[5]))
begin
  speed <= pulse_counter[6];
  pulse_counter[6] <= 1;
  int_clear[6] <= 1;
end

if(int[7] == 0)
begin
  pulse_counter[7] <= pulse_counter[7] + 1;
  int_clear[7] <= 0;
end
else if(int[7] == 1 && !(int[0]|int[1]|int[2]|int[3]|int[4]|int[5]|int[6]))
begin
  speed <= pulse_counter[7];
  pulse_counter[7] <= 1;
  int_clear[7] <= 1;
end

if(int[8] == 0)
begin
  pulse_counter[8] <= pulse_counter[8] + 1;
  int_clear[8] <= 0;
end
else if(int[8] == 1 && !(int[0]|int[1]|int[2]|int[3]|int[4]|int[5]|int[6])|int[7])
begin
  speed <= pulse_counter[8];
  pulse_counter[8] <= 1;
  int_clear[8] <= 1;
end

if(int[9] == 0)
begin
  pulse_counter[9] <= pulse_counter[9] + 1;
  int_clear[9] <= 0;
end
else if(int[9] == 1 && !(int[0]|int[1]|int[2]|int[3]|int[4]|int[5]|int[6]|int[7]|int[8]))
begin
  speed <= pulse_counter[9];
  pulse_counter[9] <= 1;
  int_clear[9] <= 1;
end*/

end
always @(posedge clki)
begin
pulse <= halla_i ^ hallb_i ^ hallc_i;
end
//------------读时序--------------//
assign READY = 1;
always @*//(posedge DSPCLKOUT)
begin
if(XRDn == 0 /*&& XZC0 == 0*/)
begin
  data <= speed;
end
end
always @(posedge clk_D)
begin
int_DSP <= halla_i;
end
assign pwm_out = pwm_in;
endmodule

yadog · 发表于 2014-6-5 11:17:15

零注释style！

先把
always@(posedge pulse)
改为上升沿探测作为使能控制信号！

sgg19964 · 发表于 2014-6-5 11:28:59

回复 2# yadog

嗯，谢谢。
“先把always@(posedge pulse)改为上升沿探测作为使能控制信号！”这个是怎么改，菜鸟不是很懂啊。

sgg19964 · 发表于 2014-6-5 12:51:58

回复 2# yadog

按以下改完没那种情况了，但是8和9丢失了
always @(posedge clk_D)
begin
F2 <= F1;
F1 <= pulse;
end
assign pulse_posedge = F1 & !F2;
always @(posedge clk_D)
begin
if(int[0] == 0 && pulse_posedge == 1)
begin
  pulse_counter[0] <= pulse_counter[0] + 1;
  int_clear[0] <= 0;
end
else if(int[0] == 1 && pulse_posedge == 1)
begin
  speed <= pulse_counter[0];
  pulse_counter[0] <= 1;
  int_clear[0] <= 1;
end

lxsuestc · 发表于 2014-6-5 13:00:01

先用modelsim跑下时序吧，修改也快

wgej1987 · 发表于 2014-6-5 14:30:01

自己好好琢磨琢磨把，搞清楚你写的每句话的实现应该很简单的

sgg19964 · 发表于 2014-6-5 15:15:44

回复 5# lxsuestc

谢谢，解决了

[求助] Verilog程序运行时序错乱了

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