Understanding the Effect of Clock Jitter on High Speed ADCs

et2234 · 发表于 2014-5-3 23:59:07

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Digitizing high speed signals to a high resolution requires careful selection of a clock that will not compromise the sampling performance of the Analog to Digital Converter (ADC). In this article we hope to give the reader a bet- ter understanding of clock jitter and how it affects the performance of the high speed ADC

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