Understanding the Effect of Clock Jitter on High Speed ADCs

et2234 · 发表于 2014-5-3 23:59:07

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Digitizing high speed signals to a high resolution requires careful selection of a clock that will not compromise the sampling performance of the Analog to Digital Converter (ADC). In this article we hope to give the reader a bet- ter understanding of clock jitter and how it affects the performance of the high speed ADC

Understanding the Effect of Clock Jitter on High Speed ADCs.pdf (107.62 KB, 下载次数: 255 )

markhorrow · 发表于 2014-5-4 13:56:47

非常感谢提供！

hnwulei · 发表于 2014-5-4 15:44:02

Clock Jitter Effects on Sampling - A Tutorial.pdf (2.21 MB)

smoun1225 · 发表于 2014-5-4 17:51:27

回复 1# et2234
感謝分享

dcircuit · 发表于 2014-5-4 20:02:25

kankan

ralphtw · 发表于 2014-6-27 18:22:49

jitter is important factor !

xuleiwx · 发表于 2014-6-28 21:59:44

是linear公司的资料。

zlhrsy · 发表于 2014-6-28 22:30:47

tks a lot

kldeng1344 · 发表于 2014-6-30 08:40:37

jitter is important factor !

fwutsairlin · 发表于 2016-4-27 17:28:37

thanks!

[资料] Understanding the Effect of Clock Jitter on High Speed ADCs

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