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Nvidia招聘,工作地点上海,有兴趣可以发简历到shww123@yeah.net
1.Position Title: ASIC design engineer Job Description/Qualifications: The ASIC design engineer is expected to co-work witharchitect to define architecture/micro-architecture, do RTL implementation andfunction verif. Minimum Requirement: - BS/MS in electrical/computer engineering and related. - Strong design/implementation skills in Verilog. - Solid understanding in feature arch and SW programmingmodel. - Good timing/power optimization skills of digital designand can drive verification on both IP and fullchip. - Perl scripting skills is appreciated as a plus. - Image process knowledge like scaling, displayPort/HDMI etcis a big plus. - Fluent English (both written and spoken) and excellentcommunication skills
- Demonstrated ability to work independently as well as in amulti-disciplinary group environment
2.Sr. PHYSICALDESIGN ENGINEER DESCRIPTION: A senior role in physical design forNVIDIA GPU and Mobile chips Participate in various aspects ofphysical design, including full chip floorplanning, power/clock distribution,timing optimization, place & route, timing closure, power/signal integrityanalysis, and physical verification Troubleshoot a wide variety of design andflow complicated issues, and apply proactive intervention Collaborate with RTL, DFT and Circuitdesigners to ensure the high quality of design implementation and optimization MINIMUMREQUIREMENTS: -
BS in Engineering or Science -
Power user of EDA tools from Synopsys (ICC/DC/PT/STAR-RC),Cadence (EDI/EPS) or Mentor (Olympus-SOC) -
Experience in Clock/Power Distribution,P&R, Timing closure, RC Extraction,and verification on 40nm, or 28nm technology -
3+ years of experience in above areas PREFERRED: -
MSin Engineering or Science -
Knowledgein 20nm or FinFET technology, circuit design, and package design -
Experiencein physical verification tools from Synopsys (ICV/Mojave) or Mentor (Calibre)
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Proficiencyin Perl, TCL and Makefile scripts
3333.Position Title: SeniorASIC Verification Engineer (Power) JobDescription/Qualifications: Responsibilities: - Developing/Maintaining verificationenvironment, including testbench, regression system - Developing test plansfor and verifying the function of ASIC power/clock control IP - Responsible for verificationcompleteness, including coverage, drive bug to close, metrics for verificationquality -Monitoring and reviewtest code Requirement: - At least 5+ years ofASIC verification experience (MS, EE) or equivalent BS EE, CE, CS. - The successful candidateshould have experience going through at least one complete and successful ASICdesign/verification cycle from architecting and creating ASIC test environmentto full completion of the verification work. - Strong programmingskills in Perl, Makefile and Verilog/Verilog-PLI/C/C++ - Working Experience withUVM/OVM/VMM (at least one of them) - A strong communicationskill in both Chinese and English is required. - Knowledge of powermanagement design/verification is a plus
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