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发表于 2014-4-28 09:51:34
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EDI最经典的入门指导帖
Assuming you are familiar with Verilog constructs, I'll explain it as follows. Assume we have a nand gate called NAND2 connected as follows:
NAND2 U42(.A(net1),.B(net2),.Q(net3));
In this case, the "U42" (the instantiation of the nand gate) would be considered the "inst", "NAND2" would be considered the "cell". "terms" and "fterms" are essentiallys "pins" but the difference is whether it is a pin of the "cell" (fterm) or the pin of the "inst" (term). The 'h' in "hinst" and "hterm" simply means it is hierarchical. For instance, say we have a top-level design "TOP" and a child "CHILD" connected as follows:
module TOP (in, out);
input in;
output out;
CHILD child_inst (.cin (in),.cout (out));
endmodule
module CHILD(cin,cout);
input cin ;
output cin;
...
endmodule
In this case, 'child_inst' would be an 'hinst' and 'child_inst/cin' would be an 'hterm'. However, 'CHILD' is still a 'cell' and 'CHILD/cin' and 'CHILD/cout' are still 'fterms'. Also note the 'TOP' is a cell and 'TOP/in' and 'TOP/out' are 'fterms'
db命名规则:
通过地址找名字. dbXXName. 比如: dbTermName
通过A地址找B地址. dbAB. 比如: dbInstTerm
通过名字找地址: dbGetXXByName 比如: dbGetInstByName
其他我一时想不起来有什么规律. |
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