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发表于 2014-4-22 14:39:09
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BUFG BUFG_reset_sync_inst (
.O(o_reset_parallel ), // 1-bit output: Clock buffer output
.I(w_reset_parallel ) // 1-bit input: Clock buffer input
);
ERRORlace:1136 - This design contains a global buffer instance,
<clk_rst_top_inst/BUFG_reset_sync_inst>, driving the net, <w_reset_parallel>,
that is driving the following (first 30) non-clock load pins.
< PIN: ctrl_channel_inst/spi_slave_inst/spi_user_logic_inst/ov_wd_data_15.SR;
>
< PIN: ccd_top_inst/ccd_vclear_inst/o_waitflag.SR; >
< PIN: ctrl_channel_inst/spi_slave_inst/spi_if_inst/rx_shift_data_33.SR; >
< PIN: ctrl_channel_inst/spi_slave_inst/spi_user_logic_inst/ov_wd_data_3.SR;
>
< PIN: ctrl_channel_inst/spi_slave_inst/spi_user_logic_inst/ov_wd_data_5.SR;
>
< PIN: ctrl_channel_inst/spi_slave_inst/spi_user_logic_inst/ov_wd_data_7.SR;
>
< PIN: ctrl_channel_inst/spi_slave_inst/spi_user_logic_inst/ov_wd_data_2.SR;
>
< PIN: ccd_top_inst/ccd_reg_inst/ov_frame_period_m_5.SR; >
< PIN: ccd_top_inst/ccd_vclear_inst/exposure_end.SR; >
< PIN: usb3_interface_top_inst/ov_usb_data_0.SR; >
< PIN: usb3_interface_top_inst/ov_usb_data_11.SR; >
< PIN: data_top_inst/ctrl_data_inst/vsync_start.SR; >
< PIN: usb3_interface_top_inst/ov_usb_data_13.SR; >
< PIN: usb3_interface_top_inst/ov_usb_data_15.SR; >
< PIN: ccd_top_inst/ccd_reg_inst/ov_frame_period_m_9.SR; >
< PIN: ccd_top_inst/ccd_reg_inst/ov_frame_period_m_7.SR; >
< PIN: ccd_top_inst/ccd_reg_inst/ov_frame_period_m_1.SR; >
< PIN: ccd_top_inst/ccd_reg_inst/ov_frame_period_m_2.SR; >
< PIN: ccd_top_inst/ccd_reg_inst/ov_frame_period_m_14.SR; >
< PIN: ccd_top_inst/ccd_reg_inst/ov_frame_period_m_12.SR; >
< PIN: ctrl_channel_inst/spi_slave_inst/spi_if_inst/o_rd_received.SR; >
< PIN: ccd_top_inst/ccd_exp_inst/xsub_last.SR; >
< PIN: usb3_interface_top_inst/frame_full_flag.SR; >
< PIN: usb3_interface_top_inst/ov_usb_data_18.SR; >
< PIN: usb3_interface_top_inst/ov_usb_data_27.SR; >
< PIN: usb3_interface_top_inst/ov_usb_data_1.SR; >
< PIN: usb3_interface_top_inst/ov_usb_data_7.SR; >
< PIN: usb3_interface_top_inst/ov_usb_data_29.SR; >
< PIN: usb3_interface_top_inst/ov_usb_data_21.SR; >
< PIN: ccd_top_inst/ccd_reg_inst/ov_frame_period_m_4.SR; >
This is not a recommended design practice in Spartan-6 due to limitations in
the global routing that may cause excessive delay, skew or unroutable
situations. It is recommended to only use a BUFG resource to drive clock
loads. If you wish to override this recommendation, you may use the
CLOCK_DEDICATED_ROUTE constraint (given below) in the .ucf file to demote
this message to a WARNING and allow your design to continue.
< PIN "clk_rst_top_inst/BUFG_reset_sync_inst.O" CLOCK_DEDICATED_ROUTE =
FALSE; >
在map阶段产生了error。翻译成中文就是说“bufg的输出只能接到时钟的负载上,不能接到FF的复位端口” |
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