社招武汉ASIC/Digital Design & Verification Engineer （内部推荐）

kgzw524

asic/Digital Design & Verification Engineer II

This position of “R&D Engineer,  II” is an ASIC/Digital Design & Verification Engineer whose mandate is to participate in the design of semiconductor integrated circuits in compliance with the project’s specifications and Synopsys’ design methodologies. The successful candidate will work on a variety of design and verification tasks, incorporating such tasks as, and not limited to, RTL coding, behavioural coding, testbench and testcase generation, RTL simulation, synthesis, STA, gate-level simulation, formal verification, documentation, and prototype evaluation.

The position requires a degree in Engineering or Applied Science (or equivalent) and 2+ years working experience in a related field as well as familiarity with both verilog circuit design and design verification and with generation of timing constraints for ASIC designs.


ASIC/Digital Design & Verification Engineer Sr I

This position of “R&D Engineer, Sr I” is an ASIC/Digital Design & Verification Engineer whose mandate is to participate in the design of semiconductor integrated circuits in compliance with the project’s specifications and Synopsys’ design methodologies. The successful candidate will work on a variety of design and verification tasks, incorporating such tasks as, and not limited to, RTL coding, behavioural coding, testbench and testcase generation, RTL simulation, synthesis, STA, gate-level simulation, formal verification, documentation, and prototype evaluation. Furthermore, the R&D Engineer, Sr I, will communicate with other Synopsys employees regarding customer technical support; may also communicate directly with customers regarding technical support; and will complete other related duties as assigned by the manager.
The successful candidate requires a degree in Engineering or Applied Science (or equivalent) and 5 years working experience in a related field as well as experience with both verilog circuit design and design verification and familiarity with generation of timing constraints for ASIC designs.

请将中英文简历发至 wang.s at 163.com 内部推荐
最好在邮件正文中用英文简单介绍自己，并说明自己适合这个职位的原因

kgzw524

昨天投递简历的朋友已经推荐，对analog和layout感兴趣的朋友也可以把简历发给我，内部也有职位空缺。另外提醒大家不要同时给多个内部员工发简历，减轻hr负担。

mooh2024

goooooooooooooooooooooooooood

mooh2024

gooooooooooooooooooooooooooooood

yesterdaym240

synopsys招聘不是春节就开始了吗，还没结束？

yesterdaym240

synopsys招聘不是春节就开始了吗，还没结束？

461159748

physical design 的还招人不？