请大神指点下 ISE14.2 用其自带的仿真软件进行仿仿真问题

gd199051

本人在VHDL方面是小白，下面的程序的激励信号怎么添加啊？
源程序：LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
ENTITY PWM IS
PORT(
     CLK:IN STD_LOGIC;
     D  :IN STD_LOGIC_VECTOR(11 DOWNTO 0);
     A  :OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
     PWMH:OUT STD_LOGIC;
     PWML:OUT STD_LOGIC
     );
END;
ARCHITECTURE BEHAVE OF PWM IS
SIGNAL PH:STD_LOGIC;
SIGNAL PL:STD_LOGIC;
SIGNAL COUNTH :STD_LOGIC_VECTOR(11 DOWNTO 0);
BEGIN
PROCESS(CLK)
BEGIN
IF CLK'EVENT AND CLK='1' AND CLK'LAST_VALUE='0' THEN
                          COUNTH<=COUNTH+'1';
       IF COUNTH="000000001111" THEN COUNTH<="000000000000";                                      
       END IF;
END IF;
IF COUNTH<=D THEN PH<='1'； PL<='0';
ELSIF COUNTH>D THEN     PH<='0'; PL<='1';
END IF;
END PROCESS ;
PWMH<=PH;
PWML<=PL;
A<=COUNTH;
END;
测试平台程序：
LIBRARY ieee;
USE ieee.std_logic_1164.ALL；
ENTITY test IS
END test;
ARCHITECTURE behavior OF test IS
    COMPONENT PWM
    PORT(
         CLK : IN  std_logic;
         D : IN  std_logic_vector(11 downto 0);
         A : OUT  std_logic_vector(11 downto 0);
         PWMH : OUT  std_logic;
         PWML : OUT  std_logic
        );
    END COMPONENT;
   --Inputs
   signal CLK : std_logic := '0';
   signal D : std_logic_vector(11 downto 0) := (others => '0');
  --Outputs
   signal A : std_logic_vector(11 downto 0);
   signal PWMH : std_logic;
   signal PWML : std_logic;
   -- Clock period definitions
   constant CLK_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
   uut: PWM PORT MAP (
          CLK => CLK,

1. 本人在VHDL方面是小白，下面的程序的激励信号怎么添加啊？
   
2. 源程序：
   
3. LIBRARY IEEE;
   
4. USE IEEE.STD_LOGIC_1164.ALL;
   
5. USE IEEE.STD_LOGIC_UNSIGNED.ALL;
   
6. USE IEEE.STD_LOGIC_ARITH.ALL;
   
7. ENTITY PWM IS
   
8. PORT(
   
9.      CLK:IN STD_LOGIC;
   
10.      D  :IN STD_LOGIC_VECTOR(11 DOWNTO 0);
    
11.      A  :OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
    
12.      PWMH:OUT STD_LOGIC;
    
13.      PWML:OUT STD_LOGIC
    
14.      );
    
15. END;
    
16. ARCHITECTURE BEHAVE OF PWM IS
    
17. SIGNAL PH:STD_LOGIC;
    
18. SIGNAL PL:STD_LOGIC;
    
19. SIGNAL COUNTH :STD_LOGIC_VECTOR(11 DOWNTO 0);
    
20. BEGIN
    
21. PROCESS(CLK)
    
22. BEGIN
    
23. IF CLK'EVENT AND CLK='1' AND CLK'LAST_VALUE='0' THEN
    
24.                           COUNTH<=COUNTH+'1';
    
25.        IF COUNTH="000000001111" THEN COUNTH<="000000000000";                                      
    
26.        END IF;
    
27. END IF;
    
28. IF COUNTH<=D THEN PH<='1';PL<='0';
    
29. ELSIF COUNTH>D THEN     PH<='0'; PL<='1';
    
30. END IF;
    
31. END PROCESS ;
    
32. PWMH<=PH;
    
33. PWML<=PL;
    
34. A<=COUNTH;
    
35. END;
    
36. 测试平台程序：
    
37. LIBRARY ieee;
    
38. USE ieee.std_logic_1164.ALL；
    
39. -- Uncomment the following library declaration if using
    
40. -- arithmetic functions with Signed or Unsigned values
    
41. --USE ieee.numeric_std.ALL;
    
42. ENTITY test IS
    
43. END test;
    
44. ARCHITECTURE behavior OF test IS
    
45.     -- Component Declaration for the Unit Under Test (UUT)
    
46.     COMPONENT PWM
    
47.     PORT(
    
48.          CLK : IN  std_logic;
    
49.          D : IN  std_logic_vector(11 downto 0);
    
50.          A : OUT  std_logic_vector(11 downto 0);
    
51.          PWMH : OUT  std_logic;
    
52.          PWML : OUT  std_logic
    
53.         );
    
54.     END COMPONENT;
    
55.    --Inputs
    
56.    signal CLK : std_logic := '0';
    
57.    signal D : std_logic_vector(11 downto 0) := (others => '0');
    
58.   --Outputs
    
59.    signal A : std_logic_vector(11 downto 0);
    
60.    signal PWMH : std_logic;
    
61.    signal PWML : std_logic;
    
62.    -- Clock period definitions
    
63.    constant CLK_period : time := 10 ns;
    
64. BEGIN
    
65. -- Instantiate the Unit Under Test (UUT)
    
66.    uut: PWM PORT MAP (
    
67.           CLK => CLK,
    
68.           D => D,
    
69.           A => A,
    
70.           PWMH => PWMH,
    
71.           PWML => PWML
    
72.         );
    
73.    -- Clock process definitions
    
74.    CLK_process :process
    
75.    begin
    
76.   CLK <= '0';
    
77.   wait for CLK_period/2;
    
78.   CLK <= '1';
    
79.   wait for CLK_period/2;
    
80.    end process;
    
81.    -- Stimulus process
    
82.    stim_proc: process
    
83.    begin  
    
84.       -- hold reset state for 100 ns.
    
85.       wait for 100 ns;
    
86.       wait for CLK_period*10;
    
87.       -- insert stimulus here
    
88.       wait;
    
89.    end process;
    
90. END;
    
91. 拜托了！！
    

复制代码

          D => D,
          A => A,
          PWMH => PWMH,
          PWML => PWML
        );
   -- Clock process definitions
   CLK_process :process
   begin
  CLK <= '0';
  wait for CLK_period/2;
  CLK <= '1';
  wait for CLK_period/2;
   end process;
   END;
拜托了！！