最近做一个ICC设计(纯数字电路),布线(六层金属)完成后用calibre做drc 发现第六层一堆问题 查看了calibre.drc(mixed signal的,FOR TSMC 0.18UM CMOS LOGIC/MS/RF AND 0.16UM CMOS LOGIC/MS 1P6M PROCESS DESIGN RULE) 有以下内容
第一套mental6规则 和icc tf相同:
// M6 checks
//=============
M6.W.1 { @ Min. M6 width < 0.44
INT M6 < 0.44 ABUT < 90 SINGULAR REGION
}
M6.S.1 { @ Min. M6 space < 0.46
EXT M6 < 0.46 ABUT < 90 SINGULAR REGION
}
M6.S.2 { @ Min. space to wide M6 (>10um) < 0.6
M6_S5 = SHRINK (SHRINK (SHRINK (SHRINK M6 RIGHT BY 5) LEFT BY 5) TOP BY 5) BOTTOM BY 5
M6_G5 = GROW (GROW (GROW (GROW M6_S5 RIGHT BY 5) LEFT BY 5) TOP BY 5) BOTTOM BY 5
M6_Wide = M6_G5 AND M6
M6_Exp = SIZE M6_Wide BY 1 INSIDE OF M6 STEP 0.322
M6_Branch = M6_Exp NOT M6_Wide
M6_Branch_edge = M6_Branch COIN INSIDE EDGE M6
M6_Check = M6 AND (SIZE M6_Exp BY 0.6)
M6_Branch_Check = M6 AND (EXPAND EDGE M6_Branch_edge OUTSIDE BY 0.6 CORNER FILL)
M6_WideC = STAMP M6_Wide BY M6xd
M6_CheckC = STAMP M6_Check BY M6xd
M6_BranchC = STAMP M6_Branch BY M6xd
M6_Branch_CheckC = STAMP M6_Branch_Check BY M6xd
EXT M6_WideC M6_CheckC < 0.6 ABUT >0 <89.5 NOT CONNECTED REGION
EXT M6_BranchC M6_Branch_CheckC < 0.6 ABUT >0 <89.5 NOT CONNECTED REGION
}
M6.E.1 { @ Min. extension of a M6 region beyond a VIA5 region < 0.09
ENC VIA5 M6 < 0.09 ABUT<90 SINGULAR
VIA5 NOT M6
}
M6.A.1 { @ Min. M6 area region < 0.562
AREA M6 < 0.562
}
第二套mental6规则 DRC报告的问题所在
#IFDEF MIX_MODE
//===============================================================================
// Mixed-Singal/RF part
//===============================================================================
// M6 checks
//=============
#IFDEF THICK_20K
.W.1 { @ Min. M6 width >= 1.50 um
INT M6 < 1.50 ABUT < 90 SINGULAR REGION
}
UTM20K.S.1 { @ Min. M6 spacing >= 1.50 um
EXT M6 < 1.50 ABUT < 90 SINGULAR REGION
}
UTM20K.E.1 { @ Min. extension of a M6 region beyond a VIA5 region >= 0.3 um
ENC VIA5 M6 < 0.3 ABUT < 90 SINGULAR REGION
VIA5 NOT M6
}
UTM20K.E.2 { @ Min. extension of M6 end-of-line region beyond VIA5 region >= 0.45 um
X = ENC [VIA5] M6 < 0.45 ABUT < 90 OPPOSITE
// a narrow side
INT X < 0.36 ABUT == 90 INTERSECTING ONLY
// adjacent narrow sides
}
UTM20K.S.2 { @ Min. space of Wide M6 (>16um) and M6 >= 3.0 um (exclude application for inductor)
M6T_NIND_S8 = SHRINK (SHRINK (SHRINK (SHRINK M6T_NIND RIGHT BY 8) LEFT BY 8) TOP BY 8) BOTTOM BY 8
M6T_NIND_G8 = GROW (GROW (GROW (GROW M6T_NIND_S8 RIGHT BY 8) LEFT BY 8) TOP BY 8) BOTTOM BY 8
M6T_NIND_Wide = M6T_NIND_G8 AND M6T_NIND
M6T_NIND_Exp = SIZE M6T_NIND_Wide BY 1 INSIDE OF M6T_NIND STEP 1.05
M6T_NIND_Branch = M6T_NIND_Exp NOT M6T_NIND_Wide
M6T_NIND_Branch_edge = M6T_NIND_Branch COIN INSIDE EDGE M6T_NIND
M6T_NIND_Check = M6T_NIND AND (SIZE M6T_NIND_Exp BY 3.0)
M6T_NIND_Branch_Check = M6T_NIND AND (EXPAND EDGE M6T_NIND_Branch_edge OUTSIDE BY 3.0 CORNER FILL)
M6T_NIND_WideC = STAMP M6T_NIND_Wide BY M6xd
M6T_NIND_CheckC = STAMP M6T_NIND_Check BY M6xd
M6T_NIND_BranchC = STAMP M6T_NIND_Branch BY M6xd
M6T_NIND_Branch_CheckC = STAMP M6T_NIND_Branch_Check BY M6xd
EXT M6T_NIND_WideC M6T_NIND_CheckC < 3.0 ABUT >0 <89.5 NOT CONNECTED REGION
EXT M6T_NIND_BranchC M6T_NIND_Branch_CheckC < 3.0 ABUT >0 <89.5 NOT CONNECTED REGION
}
UTM20K.A.1 { @ Min. area of M6 region >= 2.25 um2
AREA M6 < 2.25
}
UTM20K.R.1 { @ Min. density of M6 area >= 30% (exclude application for inductor)
CHIP_NIND = CHIP NOT INDDMY
DENSITY M6T_NIND CHIP_NIND < 0.3 PRINT M6T_DENSITY.log
[ AREA(M6T_NIND)/AREA(CHIP_NIND) ]
}