【全职】AMD 上海研发中心多岗位招聘工程师

RecruiterAMD

1.
Title: Senior GPU Performance Verification and Analysis engineer

AMD上海招聘资深工程师，请感兴趣的候选人务必以“所应聘职位_姓名_学历_专业_现公司

名称_工作年限”
为标题，把简历以附件形式发送到maggie1.zhang@amd.com,请在正文称

述应聘理由与优势。

>3 years’ experience with one of following:   a) Software: OGL/D3D driver background   b) 3D/GPU Architecture   l  c) IC Design/verification Background   l  d) CPU design/verification   l  e) 3D Application programming etc.   f) Compiler Back Ground   g) Graphics Architecture   h) GPGPU related jobs      Description of duties in addition to those in job description:   - Co-Work with World Wide Performance Verification and Analysis Team   - Plan and Execute Performance Verification and Analysis for new Project   - Continuous Team Growth   - Initiate and Lead Research on GPU architect   - Initiate Advanced Performance/Power Algorithms   - Write test plan for new graphics chips   - Write performance tests for new graphics chips   - Debug/Analysis performance bugs of graphics chips   - Debug function bugs for performance tests   - Write performance analysis tools for new graphics chips   - Function verification for new features of graphics chips   - Write benchmarks for new graphics chips   - GPGPU performance verification         Preferred Experience:   - Master Degree or Above   - 3 Years+ experience on people management   - 3 + year experience on C\C++   - Plus with experience on CPU/GPU Design/Verificaiton   - Plus with experience on Compiler   - Plus with 3+ years’ OpenGL/D3D programming experience   - Plus with 3+ years’ OpenGL/D3D driver experience   - Plus with 1+ years’ Linux/Shell   - Plus with 1+ years’ perl/python   - Familiar with Graphics Algorithm/Graphics Pipeline   - Proficient in English read/write/speaking/listening   - Good communication & Team worker

2.
MTS for ASICverification engineer

AMD上海招聘资深工程师，请感兴趣的候选人务必以“所应聘职位_姓名_学历_专业_现公司

名称_工作年限”
为标题，把简历以附件形式发送到maggie1.zhang@amd.com,请在正文称

述应聘理由与优势。

AMD System ManagementUnit(SMU) IP team delivers differentiated system management IP for all AMDproducts. You'll be working with the global team on complicated clock scheme,security processing, network on chip, power management, etc.

Requirement:

* candidate is preferredto be MSEE with minimum of 5 years, or BSEEwith minimum of 7 years experienceindigital ASIC/SOC design verification.

* deep understanding onASIC/SOC design flow

* Excellent knowledgeofdesign verification methodology, such as VMM or OVM and UVM.

* Solid experiences withsimulation model creation and the testbench build

* Strong SystemVerilogexperiences.

* Be good at scriptinglanguage, such as Perl, Cshell, Ruby, and Makefile.

* C/C++ softwaredevelopment experiences is a plus

It is a must that thecandidate has one or more of the following experience/knowledge, such asX86/ARM/8051 architecture, AMBA(AXI/AHB/APB)bus, low power design, clockgeneration and control, Legacy IPs (SPI/SMBUS/ACPI/LPC/GPIO), Generalconnectivity IPs(I2S/I2C/UART), JTAG, etc.

The candidate is expectedto exhibit good verbal and written communication skills in both Chinese andEnglish, specialized knowledge plus broad technical knowledge that facilitatesintegrative thinking, driving execution of qualityand timely result, capabilityto solve complex, novel and no-recurring problems and decision-making oncritical technical areas.

Responsibility:

* Work with designer toget a full deep insight on the design under test

* Develop stressfultestplan

* Build testbench

* Create testcase toensure maximum coverage

* Develop verification IPwhich can be reused at different levels of verfication: block level, sub-systemlevel, SoC level, etc.

3.
MTS ASIC designengineer

MTSASIC design engineer AMD System Management Unit(SMU) IP team deliversdifferentiated system management IP for all AMD products. You'll be workingwith the global team on complicated clock scheme, security processing, networkon chip, power management, etc.

Responsibility:

* Workwith Chip/IP architect to define macro-architecture specification forsub-blocks

*Implement RTL coding and communication with verification team to achieve goodcoverage

* Workwith front-end team and physical design team on timing closure

Requirement:

*Master with 6+ (or Bachelor with 8+) years working experience in ASIC area

*Familiar with Verilog HDL, Shell, Perl programming

*Knowledge on synthesis, timing analysis, CDC and formal verification

*Knowledge of AXI, ARM, NOC or security is a plus

* Goodcommunication skill and fluent English

* Goodteam player and strong sense of responsibility to deliver on time