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各位,灿芯Brite在上海和苏州开始招聘PR工程师啦!该岗位需要候选人相关工作经验在3年及以上,欢迎感兴趣的筒子投递简历至shirley.jing@britesemi.com Description: 1. Responsible for the development and support of customer based design form netlist to GDS tape out; 2. Responsible for VLSI chip floor plan; 3. Responsible for CTS, Power plan, Placement & Routing, SPF extraction; 4. Responsible for whole chip DRC/LVS, and GDS tape out. Qualification: 1. 3+ years of experience and minimum of BS in EE or equivalent; MS is a plus. Experienced in one of the major P&R (Place & Route) tool suites (Cadence, Synopsys, Mentor, or Magma); 2. Background in timing closure and signoff (PrimeTime experience); 3. Scripting expertise (Perl, Tcl, or Python) a strong plus; 4. Actual chip tapeout experience on a recent technology node (65nm or below) a strong plus. |