后端-backend engineer 简历发bestgrace@qq.com

bestgrace

后端-backend engineer 简历发bestgrace@qq.com


职位职能:  集成电路IC设计/应用工程师   
职位描述:
Position Description:
-Perform physical design implementation, including synthesis, floor planning, power grid design, place and route, clock tree synthesis, timing closure, power/signal integrity signoff, physical verification (DRC/LVS/Antenna), EM/IR signoff, DFM Closure, and physical design project management.


-The candidate will have the opportunity to work on many varieties of challenging designs, i.e. low power and high speed design. The responsibility includes participating in or leading next generation physical design, methodology and flow development.


Position Requirements:
1.BS degree with 10+ years of applicable experience, MS degree with 7+ years of applicable experience in electrical engineering, microelectronics.
2.Experienced with ASIC design flow, hierarchical physical design strategies, methodologies and understand deep sub-micron technology issues.
3.Solid knowledge on LP Design, DFT, static timing analysis, EM/IR-Drop/crosstalk analysis, formal verification, physical verification, DFM.
4.Successful track records of taping out complex, 65/40/28 nm SOC chips.
5.Automation and programming-minded, solid coding experience in Makefile/Tcl/Tk/Perl.
6. Self-motivated, able to work independently or as a team player, excellent verbal and written communication skills in English.


工作职责：  
负责从Netlist到GDS输出的后端设计工作,包括设计环境的建立,PNR library的生成及修改,芯片的布局,电源规划,单元放置,CTS,  
布线,时序分析及修正,功耗及电压完整性分析,信号完整性分析及修正,GDS输出及物理验证,DFM分析,寄生参数提取  
任职要求：  
1、微电子学专业，本科及以上学历；  
2、能独立完成从netlist到GDS signoff的后端设计工作(布局,电源规划,CTS,布线,时序修正，电压降分析，串扰，天线效应修复  
, 物理验证 ...)；  
3、三年以上后端设计经验 (有成功的65nm及以下芯片tapeout经验优先)；  
4、精通后端主流EDA工具 (Cadence/Synopsys/Mentor)；  
5、熟悉UNIX/LINUX操作系统,熟悉Tcl、pearl、shell编程；
注意期望地点是上海  
Grace Li @ Hi-Talent Consulting Co. , Ltd.
上海芯相会企业管理咨询有限公司
上海芯得企业管理咨询有限公司
E-Mail: bestgrace@qq.com
QQ: 2862465331
新浪blog: http://blog.sina.com.cn/u/1767088102

新浪微博:http://weibo.com/bestgrace