Verification Engineer--高级IC职位--猎头推荐

沪上小白

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Verification Engineer

Location: BJ

PositionDescription:

Deliver/implement advanced verificationsolutions by utilizing Incisive Verification product portfolio. The engineershould be able to act as a strong team member and contributor, leading teamprojects and initiatives. Exercise judgment within generally defined practicesand policies.

Specific duties include:

--Deep understanding on ASIC/SOC designflow

--Excellent knowledge of advancedverification methodology like eRM/OVM/UVM

–Familiarwith Incisive Plan to Closure Methodology (IPCM)

--Proficiency in System Verilog, System Cand/or e (Specman)

–Developingand using Verification Components (eVC,OVC,UVC,VIP)

–Developingand using assertion based verification and formal analysis methods

--Skilled in scripting language,such asPerl,C shell,Python,Makefile

–Assessingthe project verification requirements

–Operatingin a lead role regarding architecting and implementation of project verificationenvironment/solution.

–Maycoordinate/lead others within the scope of a defined project

PositionRequirements:

Essential Qualifications:

- BS degree with 5+ years of applicableexperience,MS degree with 4+ years of applicable experience in electricalengineering,microelectronics,comparable engineering science or solid statephysics.

- Essential that the individualdemonstrates strong communication,verbal and written. Requires goodcommunication skills in English.

Desirable Qualifications:

- A minimum of four years relevantexperience in industry.

- Will have demonstrated hands-onexperience and expertise with verification design tools or equivalent tools,flows and methodologies required to execute a verification project.

- Will have demonstrated successfulcompletion of 6+ verification projects as an individual contributor

- Will have DDR project verificationexperience