Compact Models for Future Generation CMOS

Areky

UC Berkeley PHD Thesis

Enjoy ~

Contents
Contents ii
Acknowledgements vi
1 Introduction 1
1.1 CMOS Scaling and its Challenges . . . ..................... 1
1.2 Multi-gateMOSFET—theFutureCMOSTransistorStructure ....... 2
1.2.1 AdvantagesofMulti-gateMOSFETs .................. 2
1.2.2 VariousFlavorsofMulti-gateMOSFET ................ 2
1.3 Multi-gateCMOSModeling ........................... 3
1.3.1 BSIM-MG: A family of BSIM Models for Multi-gate MOSFET . . . 3
1.3.2 BSIM-IMGandBSIM-CMG....................... 5
1.4 Modeling Parasitic Resistances and Capacitances in the FinFET Multi-Gate
Device ....................................... 5
1.5 VariationinFinFETSRAMCells........................ 6
1.6 Thermal Noise Modeling for Planar and Multi-gate Transistors ........ 7
1.7 Dissertation Goals and Outline ......................... 7
2 Basic Formulations of Multiple-Gate MOSFET Compact Models 9
2.1 CoreModelsofBSIM-CMGandBSIM-IMG.................. 9
2.2 Modeling Double-gate Fully-depleted SOI MOSFETs with BSIM-IMG .... 10
2.3 CoreModelofBSIM-IMG............................ 11
2.3.1 Modeling Framework ........................... 11
2.3.2 Explicit Approximation for Surface Potential .............. 11
2.3.3 DrainCurrentModel........................... 15
2.3.4 CapacitanceModel ............................ 23
2.4 CoreModelofBSIM-CMG............................ 24
2.4.1 Background ................................ 24
2.4.2 Simple Non Charge Sheet I-V Model .................. 26
2.5 Real Device Effects and Source Drain Symmetry ................ 28
2.6 ModelConvergence................................ 30
2.7 Computational Efficiency Study ......................... 33
2.7.1 EvaluationMethodology ......................... 33
2.7.2 Computational Efficiency of Surface Potential Calculation in BSIM-
CMG.................................... 35
2.7.3 Computational Efficiency of Surface Potential Calculation in BSIM-IMG 35
2.8 CircuitSimulationusingBSIM-IMGandBSIM-CMG............. 37
2.8.1 FinFETSRAMwithBack-gateDynamicFeedback .......... 37
2.8.2 Dynamic Threshold Voltage Tuning to Combat Variation in Back-
gatedFDSOI ............................... 38
2.9 Summary ..................................... 38
3 Symmetry in MOSFET Compact Models 41
3.1 Symmetry Definition and the Gummel Symmetry Test ............ 41
3.2 SymmetryofMOSFETCoreModels ...................... 42
3.2.1 SquareLawModel ............................ 42
3.2.2 BSIM-IMGCoreModel ......................... 43
3.2.3 BSIM-CMGCoreModel ......................... 43
3.3 Rules for Incorporating Real Device Effects ................... 44
3.4 Relation of Source/Drain Swapping and Continuity .............. 48
3.5 Discussion on the Formulation of Effective Drain-to-source Voltage ...... 49
3.6 Summary ..................................... 49
4 Modeling of FinFET Parasitic Source and Drain Resistances 52
4.1 FinFET Device Structure and Symbol Definitions . . . ............ 53
4.2 Modeling of Geometry Dependent Source/Drain Resistances in FinFETs . . 57
4.2.1 ContactResistance ............................ 57
4.2.2 Spreading Resistance ........................... 59
4.2.3 ExtensionResistance........................... 62
4.3 Verification .................................... 65
4.3.1 TCADSimulationSetup......................... 65
4.3.2 Device Optimization ........................... 68
4.3.3 Extraction of Source and Drain Resistances .............. 68
4.4 Discussion..................................... 74
4.5 Conclusion..................................... 76
5 Compact Modeling of Variation in FinFET SRAM Cells 77
5.1 Introduction.................................... 77
5.2 SRAMDesignConsiderations .......................... 78
5.3 FinFETSRAMAdvantagesandChallenges .................. 81
5.4 Modeling Vth Variation due to Gate Length and Fin Thickness Variation . . 81
5.5 Modeling Variation in SRAM Cells ....................... 82
5.6 StatisticalDesignProcedureforFinFETSRAMs ............... 83
5.7 ExperimentalVerification ............................ 85
5.7.1 DeviceFabrication ............................ 85
5.7.2 Nominal Parameter Extraction ..................... 85
5.7.3 AdjustmentforSRAMFETs ...................... 85
5.7.4 Calibration of Variation ......................... 85
5.8 FinFETSRAMCellDesignExercise ...................... 89
5.8.1 DesignCriterionforReadandWriteOperations............ 89
5.8.2 Cell Optimization ............................. 89
5.9 SensitivityAnalysis................................ 91
5.10 Improved Variation Calibration Method .................... 91
5.11Conclusion..................................... 94
6 Thermal Noise Modeling for BSIM4 and BSIM-MG 95
6.1 Review:BSIM4Thermalnoisemodel...................... 96
6.1.1 Charge-BasedThermalNoiseModel................... 96
6.1.2 HolisticThermalNoiseModel ...................... 97
6.1.3 VerificationwithCircuitSimulation................... 101
6.2 DerivationofNewThermalNoiseModel .................... 101
6.2.1 DrainNoise ................................ 103
6.2.2 InducedGateNoise............................ 105
6.2.3 Correlation ................................ 106
6.2.4 Verification ................................ 107
6.3 ThermalNoiseintheWeakInversionRegion.................. 109
6.3.1 Derivation of Thermal Noise Expressions Valid in All Regions of Op-
eration................................... 112
6.3.2 Verifications................................ 115
6.4 Implementing Correlated Noise Sources in SPICE3 .............. 118
6.4.1 Implementation.............................. 118
6.4.2 Verification ................................ 119
6.5 Modeling Excess Noise for Short Channel Devices ............... 121
6.6 Thermal Noise Modeling for BSIM-MG ..................... 125
6.7 ConclusionandFutureWork........................... 125
7 Conclusions 127
7.1 Summary and Future Research Directions ................... 127
7.1.1 IndependentMulti-gateMOSFETModelBSIM-IMG ......... 127
7.1.2 CommonMulti-gateMOSFETModelBSIM-CMG .......... 128
7.1.3 SymmetryofMOSFETCompactModels................ 128
7.1.4 Modeling Source and Drain Resistances for the FinFET ........ 129
7.1.5 Compact Modeling of Variation in FinFETs .............. 129
7.1.6 Thermal Noise Modeling ......................... 129
7.2 Conclusion..................................... 130
Bibliography 131
A Back Surface Potential and Inversion Charge Calculation in BSIM-IMG 142
B Monte Carlo Based Framework for FinFET SRAM Variation Simulation 146
C Simple Segmentable BSIM 148
D Code Listing: Evaluating Output Noise Contribution of Correlated Noise
Sources 154

waveguides

有些日子了。不过做电路确实应该知道些模型及其相关的东西。

markhorrow

非常感谢提供！

yhs-ic

正需要了解，多谢楼主

qpf_rf

谢谢

ljcfcb

牛~，刚好可以拿过来学习一下

john_123

thanks

ppsa

thanks

skahill

Thanks

purpleside

学习一下