马上注册，结交更多好友，享用更多功能，让你轻松玩转社区。
您需要 登录 才可以下载或查看，没有账号？注册
x
`timescale 1 ns / 1ps
module dvi_decoder (
input wire tmdsclk_p, // tmds clock
input wire tmdsclk_n, // tmds clock
input wire blue_p, // Blue data in
input wire green_p, // Green data in
input wire red_p, // Red data in
input wire blue_n, // Blue data in
input wire green_n, // Green data in
input wire red_n, // Red data in
input wire exrst, // external reset input, e.g. reset button
output wire reset, // rx reset
output wire pclk, // regenerated pixel clock
// output wire pclkx2, // double rate pixel clock
// output wire pclkx10, // 10x pixel as IOCLK
// output wire pllclk0, // send pllclk0 out so it can be fed into a different BUFPLL
// output wire pllclk1, // PLL x1 output
// output wire pllclk2, // PLL x2 output
//
// output wire pll_lckd, // send pll_lckd out so it can be fed into a different BUFPLL
// output wire serdesstrobe, // BUFPLL serdesstrobe output
// output wire tmdsclk, // TMDS cable clock
output wire hsync, // hsync data
output wire vsync, // vsync data
output wire de, // data enable
// output wire blue_vld,
// output wire green_vld,
// output wire red_vld,
// output wire blue_rdy,
// output wire green_rdy,
// output wire red_rdy,
// output wire psalgnerr,
// output wire [29:0] sdout,
output wire [7:0] red, // pixel data out
output wire [7:0] green, // pixel data out
output wire [7:0] blue); // pixel data out
//---------------
wire blue_vld;
wire green_vld;
wire red_vld;
wire blue_rdy;
wire green_rdy;
wire red_rdy;
wire psalgnerr;
wire [29:0] sdout;
wire pclkx2; // double rate pixel clock
wire pclkx10; // 10x pixel as IOCLK
wire pllclk0; // send pllclk0 out so it can be fed into a different BUFPLL
wire pllclk1; // PLL x1 output
wire pllclk2; // PLL x2 output
wire pll_lckd; // send pll_lckd out so it can be fed into a different BUFPLL
wire serdesstrobe; // BUFPLL serdesstrobe output
wire tmdsclk; // TMDS cable clock
//---------------
wire [9:0] sdout_blue, sdout_green, sdout_red;
/*
assign sdout = {sdout_red[9], sdout_green[9], sdout_blue[9], sdout_red[8], sdout_green[8], sdout_blue[8],
sdout_red[7], sdout_green[7], sdout_blue[7], sdout_red[6], sdout_green[6], sdout_blue[6],
sdout_red[5], sdout_green[5], sdout_blue[5], sdout_red[4], sdout_green[4], sdout_blue[4],
sdout_red[3], sdout_green[3], sdout_blue[3], sdout_red[2], sdout_green[2], sdout_blue[2],
sdout_red[1], sdout_green[1], sdout_blue[1], sdout_red[0], sdout_green[0], sdout_blue[0]} ;
*/
assign sdout = {sdout_red[9:5], sdout_green[9:5], sdout_blue[9:5],
sdout_red[4:0], sdout_green[4:0], sdout_blue[4:0]};
wire de_b, de_g, de_r;
assign de = de_b;
//wire blue_vld, green_vld, red_vld;
//wire blue_rdy, green_rdy, red_rdy;
wire blue_psalgnerr, green_psalgnerr, red_psalgnerr;
//
// Send TMDS clock to a differential buffer and then a BUFIO2
// This is a required path in Spartan-6 feed a PLL CLKIN
//
wire rxclkint;
IBUFDS #(.IOSTANDARD("TMDS_33"), .DIFF_TERM("FALSE")
) ibuf_rxclk (.I(tmdsclk_p), .IB(tmdsclk_n), .O(rxclkint));
wire rxclk;
BUFIO2 #(.DIVIDE_BYPASS("TRUE"), .DIVIDE(1))
bufio_tmdsclk (.DIVCLK(rxclk), .IOCLK(), .SERDESSTROBE(), .I(rxclkint));
BUFG tmdsclk_bufg (.I(rxclk), .O(tmdsclk));
//
// PLL is used to generate three clocks:
// 1. pclk: same rate as TMDS clock
// 2. pclkx2: double rate of pclk used for 5:10 soft gear box and ISERDES DIVCLK
// 3. pclkx10: 10x rate of pclk used as IO clock
//
PLL_BASE # (
.CLKIN_PERIOD(10),
.CLKFBOUT_MULT(10), //set VCO to 10x of CLKIN
.CLKOUT0_DIVIDE(1),
.CLKOUT1_DIVIDE(10),
.CLKOUT2_DIVIDE(5),
.COMPENSATION("INTERNAL")
) PLL_ISERDES (
.CLKFBOUT(clkfbout),
.CLKOUT0(pllclk0),
.CLKOUT1(pllclk1),
.CLKOUT2(pllclk2),
.CLKOUT3(),
.CLKOUT4(),
.CLKOUT5(),
.LOCKED(pll_lckd),
.CLKFBIN(clkfbout),
.CLKIN(rxclk),
.RST(exrst)
);
//
// Pixel Rate clock buffer
//
BUFG pclkbufg (.I(pllclk1), .O(pclk));
//////////////////////////////////////////////////////////////////
// 2x pclk is going to be used to drive IOSERDES2 DIVCLK
//////////////////////////////////////////////////////////////////
BUFG pclkx2bufg (.I(pllclk2), .O(pclkx2));
//////////////////////////////////////////////////////////////////
// 10x pclk is used to drive IOCLK network so a bit rate reference
// can be used by IOSERDES2
//////////////////////////////////////////////////////////////////
wire bufpll_lock;
BUFPLL #(.DIVIDE(5)) ioclk_buf (.PLLIN(pllclk0), .GCLK(pclkx2), .LOCKED(pll_lckd),
.IOCLK(pclkx10), .SERDESSTROBE(serdesstrobe), .LOCK(bufpll_lock));
assign reset = ~bufpll_lock;
decode dec_b (
.reset (reset),
.pclk (pclk),
.pclkx2 (pclkx2),
.pclkx10 (pclkx10),
.serdesstrobe (serdesstrobe),
.din_p (blue_p),
.din_n (blue_n),
.other_ch0_rdy(green_rdy),
.other_ch1_rdy(red_rdy),
.other_ch0_vld(green_vld),
.other_ch1_vld(red_vld),
.iamvld (blue_vld),
.iamrdy (blue_rdy),
.psalgnerr (blue_psalgnerr),
.c0 (hsync),
.c1 (vsync),
.de (de_b),
.sdout (sdout_blue),
.dout (blue)) ;
decode dec_g (
.reset (reset),
.pclk (pclk),
.pclkx2 (pclkx2),
.pclkx10 (pclkx10),
.serdesstrobe (serdesstrobe),
.din_p (green_p),
.din_n (green_n),
.other_ch0_rdy(blue_rdy),
.other_ch1_rdy(red_rdy),
.other_ch0_vld(blue_vld),
.other_ch1_vld(red_vld),
.iamvld (green_vld),
.iamrdy (green_rdy),
.psalgnerr (green_psalgnerr),
.c0 (),
.c1 (),
.de (de_g),
.sdout (sdout_green),
.dout (green)) ;
decode dec_r (
.reset (reset),
.pclk (pclk),
.pclkx2 (pclkx2),
.pclkx10 (pclkx10),
.serdesstrobe (serdesstrobe),
.din_p (red_p),
.din_n (red_n),
.other_ch0_rdy(blue_rdy),
.other_ch1_rdy(green_rdy),
.other_ch0_vld(blue_vld),
.other_ch1_vld(green_vld),
.iamvld (red_vld),
.iamrdy (red_rdy),
.psalgnerr (red_psalgnerr),
.c0 (),
.c1 (),
.de (de_r),
.sdout (sdout_red),
.dout (red)) ;
assign psalgnerr = red_psalgnerr | blue_psalgnerr | green_psalgnerr;
endmodule |
/2 
eetop公众号
创芯大讲堂
创芯人才网
发表于 2014-1-14 15:04:31
