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Fdatool 数字滤波器设计,Matlab生产的Verilog 模块中
// -------------------------------------------------------------
//
// Module: filter
// Generated by MATLAB(R) 8.1 and the Filter Design HDL Coder 2.9.3.
// Generated on: 2013-12-15 07:36:05
// -------------------------------------------------------------
// -------------------------------------------------------------
// HDL Code Generation Options:
//
// TargetDirectory: E:\foct\modelsim\fir
// InputPort: filter_in2
// OutputPort: filter_out2
// ResetAssertedLevel: Active-low
// TargetLanguage: Verilog
// TestBenchStimulus: impulse step ramp chirp noise
// -------------------------------------------------------------
// HDL Implementation : Fully parallel
// Multipliers : 51
// Folding Factor : 1
// -------------------------------------------------------------
// Filter Settings:
//
// Discrete-Time FIR Filter (real)
// -------------------------------
// Filter Structure : Direct-Form FIR
// Filter Length : 51
// Stable : Yes
// Linear Phase : Yes (Type 1)
// -------------------------------------------------------------
`timescale 1 ns / 1 ns
module filter
(
clk,
clk_enable,
reset,
filter_in2,
filter_out2
);
input clk;
input clk_enable;
input reset;
input [63:0] filter_in2; //double
output [63:0] filter_out2; //double
////////////////////////////////////////////////////////////////
//Module Architecture: filter
////////////////////////////////////////////////////////////////
// Local Functions
// Type Definitions
// Constants
parameter coeff1 = -9.1909820848023365E-04; //double
parameter coeff2 = -2.7176960266135104E-03; //double
parameter coeff3 = -2.4869527598547769E-03; //double
parameter coeff4 = 3.6614383834880021E-03; //double
parameter coeff5 = 1.3650925230654665E-02; //double
parameter coeff6 = 1.7351165901097833E-02; //double
parameter coeff7 = 7.6653061904350282E-03; //double
parameter coeff8 = -6.5547188696257405E-03; //double
parameter coeff9 = -7.6967840370497712E-03; //double
parameter coeff10 = 6.1054594214059428E-03; //double
parameter coeff11 = 1.3873915748642274E-02; //double
parameter coeff12 = 3.5086172829529847E-04; //double
parameter coeff13 = -1.6908925436685863E-02; //double
parameter coeff14 = -8.9056427491535015E-03; //double
parameter coeff15 = 1.7441129500859021E-02; //double
parameter coeff16 = 2.0745044527611053E-02; //double
parameter coeff17 = -1.2296494251941101E-02; //double
parameter coeff18 = -3.4240865909579483E-02; //double
parameter coeff19 = -1.0345296055731883E-03; //double
parameter coeff20 = 4.7790305520800068E-02; //double
parameter coeff21 = 2.7363037914845938E-02; //double
parameter coeff22 = -5.9379518831047785E-02; //double
parameter coeff23 = -8.2307025929228714E-02; //double
parameter coeff24 = 6.7186909432870909E-02; //double
parameter coeff25 = 3.1001517709024962E-01; //double
parameter coeff26 = 4.3004788034351460E-01; //double
parameter coeff27 = 3.1001517709024962E-01; //double
parameter coeff28 = 6.7186909432870909E-02; //double
parameter coeff29 = -8.2307025929228714E-02; //double
parameter coeff30 = -5.9379518831047785E-02; //double
parameter coeff31 = 2.7363037914845938E-02; //double
parameter coeff32 = 4.7790305520800068E-02; //double
parameter coeff33 = -1.0345296055731883E-03; //double
parameter coeff34 = -3.4240865909579483E-02; //double
parameter coeff35 = -1.2296494251941101E-02; //double
parameter coeff36 = 2.0745044527611053E-02; //double
parameter coeff37 = 1.7441129500859021E-02; //double
parameter coeff38 = -8.9056427491535015E-03; //double
parameter coeff39 = -1.6908925436685863E-02; //double
parameter coeff40 = 3.5086172829529847E-04; //double
parameter coeff41 = 1.3873915748642274E-02; //double
parameter coeff42 = 6.1054594214059428E-03; //double
parameter coeff43 = -7.6967840370497712E-03; //double
parameter coeff44 = -6.5547188696257405E-03; //double
parameter coeff45 = 7.6653061904350282E-03; //double
parameter coeff46 = 1.7351165901097833E-02; //double
parameter coeff47 = 1.3650925230654665E-02; //double
parameter coeff48 = 3.6614383834880021E-03; //double
parameter coeff49 = -2.4869527598547769E-03; //double
parameter coeff50 = -2.7176960266135104E-03; //double
parameter coeff51 = -9.1909820848023365E-04; //double
// Signals
real delay_pipeline [0:50] ; // double
real product51; // double
real product50; // double
real product49; // double
real product48; // double
real product47; // double
real product46; // double
real product45; // double
real product44; // double
real product43; // double
real product42; // double
real product41; // double
real product40; // double
real product39; // double
real product38; // double
real product37; // double
real product36; // double
real product35; // double
real product34; // double
real product33; // double
real product32; // double
real product31; // double
real product30; // double
real product29; // double
real product28; // double
real product27; // double
real product26; // double
real product25; // double
real product24; // double
real product23; // double
real product22; // double
real product21; // double
real product20; // double
real product19; // double
real product18; // double
real product17; // double
real product16; // double
real product15; // double
real product14; // double
real product13; // double
real product12; // double
real product11; // double
real product10; // double
real product9; // double
real product8; // double
real product7; // double
real product6; // double
real product5; // double
real product4; // double
real product3; // double
real product2; // double
real product1_cast; // double
real product1; // double
real sum1; // double
real sum2; // double
real sum3; // double
real sum4; // double
real sum5; // double
real sum6; // double
real sum7; // double
real sum8; // double
real sum9; // double
real sum10; // double
real sum11; // double
real sum12; // double
real sum13; // double
real sum14; // double
real sum15; // double
real sum16; // double
real sum17; // double
real sum18; // double
real sum19; // double
real sum20; // double
real sum21; // double
real sum22; // double
real sum23; // double
real sum24; // double
real sum25; // double
real sum26; // double
real sum27; // double
real sum28; // double
real sum29; // double
real sum30; // double
real sum31; // double
real sum32; // double
real sum33; // double
real sum34; // double
real sum35; // double
real sum36; // double
real sum37; // double
real sum38; // double
real sum39; // double
real sum40; // double
real sum41; // double
real sum42; // double
real sum43; // double
real sum44; // double
real sum45; // double
real sum46; // double
real sum47; // double
real sum48; // double
real sum49; // double
real sum50; // double
real output_typeconvert; // double
real output_register; // double
// Block Statements
always @( posedge clk or negedge reset)
begin: Delay_Pipeline_process
if (reset == 1'b0) begin
delay_pipeline[0] <= 0.0000000000000000E+00;
delay_pipeline[1] <= 0.0000000000000000E+00;
delay_pipeline[2] <= 0.0000000000000000E+00;
delay_pipeline[3] <= 0.0000000000000000E+00;
delay_pipeline[4] <= 0.0000000000000000E+00;
delay_pipeline[5] <= 0.0000000000000000E+00;
delay_pipeline[6] <= 0.0000000000000000E+00;
delay_pipeline[7] <= 0.0000000000000000E+00;
delay_pipeline[8] <= 0.0000000000000000E+00;
delay_pipeline[9] <= 0.0000000000000000E+00;
delay_pipeline[10] <= 0.0000000000000000E+00;
delay_pipeline[11] <= 0.0000000000000000E+00;
delay_pipeline[12] <= 0.0000000000000000E+00;
delay_pipeline[13] <= 0.0000000000000000E+00;
delay_pipeline[14] <= 0.0000000000000000E+00;
delay_pipeline[15] <= 0.0000000000000000E+00;
delay_pipeline[16] <= 0.0000000000000000E+00;
delay_pipeline[17] <= 0.0000000000000000E+00;
delay_pipeline[18] <= 0.0000000000000000E+00;
delay_pipeline[19] <= 0.0000000000000000E+00;
delay_pipeline[20] <= 0.0000000000000000E+00;
delay_pipeline[21] <= 0.0000000000000000E+00;
delay_pipeline[22] <= 0.0000000000000000E+00;
delay_pipeline[23] <= 0.0000000000000000E+00;
delay_pipeline[24] <= 0.0000000000000000E+00;
delay_pipeline[25] <= 0.0000000000000000E+00;
delay_pipeline[26] <= 0.0000000000000000E+00;
delay_pipeline[27] <= 0.0000000000000000E+00;
delay_pipeline[28] <= 0.0000000000000000E+00;
delay_pipeline[29] <= 0.0000000000000000E+00;
delay_pipeline[30] <= 0.0000000000000000E+00;
delay_pipeline[31] <= 0.0000000000000000E+00;
delay_pipeline[32] <= 0.0000000000000000E+00;
delay_pipeline[33] <= 0.0000000000000000E+00;
delay_pipeline[34] <= 0.0000000000000000E+00;
delay_pipeline[35] <= 0.0000000000000000E+00;
delay_pipeline[36] <= 0.0000000000000000E+00;
delay_pipeline[37] <= 0.0000000000000000E+00;
delay_pipeline[38] <= 0.0000000000000000E+00;
delay_pipeline[39] <= 0.0000000000000000E+00;
delay_pipeline[40] <= 0.0000000000000000E+00;
delay_pipeline[41] <= 0.0000000000000000E+00;
delay_pipeline[42] <= 0.0000000000000000E+00;
delay_pipeline[43] <= 0.0000000000000000E+00;
delay_pipeline[44] <= 0.0000000000000000E+00;
delay_pipeline[45] <= 0.0000000000000000E+00;
delay_pipeline[46] <= 0.0000000000000000E+00;
delay_pipeline[47] <= 0.0000000000000000E+00;
delay_pipeline[48] <= 0.0000000000000000E+00;
delay_pipeline[49] <= 0.0000000000000000E+00;
delay_pipeline[50] <= 0.0000000000000000E+00;
end
else begin
if (clk_enable == 1'b1) begin
delay_pipeline[0] <= $bitstoreal(filter_in2);
delay_pipeline[1] <= delay_pipeline[0];
delay_pipeline[2] <= delay_pipeline[1];
delay_pipeline[3] <= delay_pipeline[2];
delay_pipeline[4] <= delay_pipeline[3];
delay_pipeline[5] <= delay_pipeline[4];
delay_pipeline[6] <= delay_pipeline[5];
delay_pipeline[7] <= delay_pipeline[6];
delay_pipeline[8] <= delay_pipeline[7];
delay_pipeline[9] <= delay_pipeline[8];
delay_pipeline[10] <= delay_pipeline[9];
delay_pipeline[11] <= delay_pipeline[10];
delay_pipeline[12] <= delay_pipeline[11];
delay_pipeline[13] <= delay_pipeline[12];
delay_pipeline[14] <= delay_pipeline[13];
delay_pipeline[15] <= delay_pipeline[14];
delay_pipeline[16] <= delay_pipeline[15];
delay_pipeline[17] <= delay_pipeline[16];
delay_pipeline[18] <= delay_pipeline[17];
delay_pipeline[19] <= delay_pipeline[18];
delay_pipeline[20] <= delay_pipeline[19];
delay_pipeline[21] <= delay_pipeline[20];
delay_pipeline[22] <= delay_pipeline[21];
delay_pipeline[23] <= delay_pipeline[22];
delay_pipeline[24] <= delay_pipeline[23];
delay_pipeline[25] <= delay_pipeline[24];
delay_pipeline[26] <= delay_pipeline[25];
delay_pipeline[27] <= delay_pipeline[26];
delay_pipeline[28] <= delay_pipeline[27];
delay_pipeline[29] <= delay_pipeline[28];
delay_pipeline[30] <= delay_pipeline[29];
delay_pipeline[31] <= delay_pipeline[30];
delay_pipeline[32] <= delay_pipeline[31];
delay_pipeline[33] <= delay_pipeline[32];
delay_pipeline[34] <= delay_pipeline[33];
delay_pipeline[35] <= delay_pipeline[34];
delay_pipeline[36] <= delay_pipeline[35];
delay_pipeline[37] <= delay_pipeline[36];
delay_pipeline[38] <= delay_pipeline[37];
delay_pipeline[39] <= delay_pipeline[38];
delay_pipeline[40] <= delay_pipeline[39];
delay_pipeline[41] <= delay_pipeline[40];
delay_pipeline[42] <= delay_pipeline[41];
delay_pipeline[43] <= delay_pipeline[42];
delay_pipeline[44] <= delay_pipeline[43];
delay_pipeline[45] <= delay_pipeline[44];
delay_pipeline[46] <= delay_pipeline[45];
delay_pipeline[47] <= delay_pipeline[46];
delay_pipeline[48] <= delay_pipeline[47];
delay_pipeline[49] <= delay_pipeline[48];
delay_pipeline[50] <= delay_pipeline[49];
end
end
end // Delay_Pipeline_process
always @* product51 <= delay_pipeline[50] * coeff51;
always @* product50 <= delay_pipeline[49] * coeff50;
always @* product49 <= delay_pipeline[48] * coeff49;
always @* product48 <= delay_pipeline[47] * coeff48;
always @* product47 <= delay_pipeline[46] * coeff47;
always @* product46 <= delay_pipeline[45] * coeff46;
always @* product45 <= delay_pipeline[44] * coeff45;
always @* product44 <= delay_pipeline[43] * coeff44;
always @* product43 <= delay_pipeline[42] * coeff43;
always @* product42 <= delay_pipeline[41] * coeff42;
always @* product41 <= delay_pipeline[40] * coeff41;
always @* product40 <= delay_pipeline[39] * coeff40;
always @* product39 <= delay_pipeline[38] * coeff39;
always @* product38 <= delay_pipeline[37] * coeff38;
always @* product37 <= delay_pipeline[36] * coeff37;
always @* product36 <= delay_pipeline[35] * coeff36;
always @* product35 <= delay_pipeline[34] * coeff35;
always @* product34 <= delay_pipeline[33] * coeff34;
always @* product33 <= delay_pipeline[32] * coeff33;
always @* product32 <= delay_pipeline[31] * coeff32;
always @* product31 <= delay_pipeline[30] * coeff31;
always @* product30 <= delay_pipeline[29] * coeff30;
always @* product29 <= delay_pipeline[28] * coeff29;
always @* product28 <= delay_pipeline[27] * coeff28;
always @* product27 <= delay_pipeline[26] * coeff27;
always @* product26 <= delay_pipeline[25] * coeff26;
always @* product25 <= delay_pipeline[24] * coeff25;
always @* product24 <= delay_pipeline[23] * coeff24;
always @* product23 <= delay_pipeline[22] * coeff23;
always @* product22 <= delay_pipeline[21] * coeff22;
always @* product21 <= delay_pipeline[20] * coeff21;
always @* product20 <= delay_pipeline[19] * coeff20;
always @* product19 <= delay_pipeline[18] * coeff19;
always @* product18 <= delay_pipeline[17] * coeff18;
always @* product17 <= delay_pipeline[16] * coeff17;
always @* product16 <= delay_pipeline[15] * coeff16;
always @* product15 <= delay_pipeline[14] * coeff15;
always @* product14 <= delay_pipeline[13] * coeff14;
always @* product13 <= delay_pipeline[12] * coeff13;
always @* product12 <= delay_pipeline[11] * coeff12;
always @* product11 <= delay_pipeline[10] * coeff11;
always @* product10 <= delay_pipeline[9] * coeff10;
always @* product9 <= delay_pipeline[8] * coeff9;
always @* product8 <= delay_pipeline[7] * coeff8;
always @* product7 <= delay_pipeline[6] * coeff7;
always @* product6 <= delay_pipeline[5] * coeff6;
always @* product5 <= delay_pipeline[4] * coeff5;
always @* product4 <= delay_pipeline[3] * coeff4;
always @* product3 <= delay_pipeline[2] * coeff3;
always @* product2 <= delay_pipeline[1] * coeff2;
always @* product1_cast <= product1;
always @* product1 <= delay_pipeline[0] * coeff1;
always @* sum1 <= product1_cast + product2;
always @* sum2 <= sum1 + product3;
always @* sum3 <= sum2 + product4;
always @* sum4 <= sum3 + product5;
always @* sum5 <= sum4 + product6;
always @* sum6 <= sum5 + product7;
always @* sum7 <= sum6 + product8;
always @* sum8 <= sum7 + product9;
always @* sum9 <= sum8 + product10;
always @* sum10 <= sum9 + product11;
always @* sum11 <= sum10 + product12;
always @* sum12 <= sum11 + product13;
always @* sum13 <= sum12 + product14;
always @* sum14 <= sum13 + product15;
always @* sum15 <= sum14 + product16;
always @* sum16 <= sum15 + product17;
always @* sum17 <= sum16 + product18;
always @* sum18 <= sum17 + product19;
always @* sum19 <= sum18 + product20;
always @* sum20 <= sum19 + product21;
always @* sum21 <= sum20 + product22;
always @* sum22 <= sum21 + product23;
always @* sum23 <= sum22 + product24;
always @* sum24 <= sum23 + product25;
always @* sum25 <= sum24 + product26;
always @* sum26 <= sum25 + product27;
always @* sum27 <= sum26 + product28;
always @* sum28 <= sum27 + product29;
always @* sum29 <= sum28 + product30;
always @* sum30 <= sum29 + product31;
always @* sum31 <= sum30 + product32;
always @* sum32 <= sum31 + product33;
always @* sum33 <= sum32 + product34;
always @* sum34 <= sum33 + product35;
always @* sum35 <= sum34 + product36;
always @* sum36 <= sum35 + product37;
always @* sum37 <= sum36 + product38;
always @* sum38 <= sum37 + product39;
always @* sum39 <= sum38 + product40;
always @* sum40 <= sum39 + product41;
always @* sum41 <= sum40 + product42;
always @* sum42 <= sum41 + product43;
always @* sum43 <= sum42 + product44;
always @* sum44 <= sum43 + product45;
always @* sum45 <= sum44 + product46;
always @* sum46 <= sum45 + product47;
always @* sum47 <= sum46 + product48;
always @* sum48 <= sum47 + product49;
always @* sum49 <= sum48 + product50;
always @* sum50 <= sum49 + product51;
always @* output_typeconvert <= sum50;
always @ (posedge clk or negedge reset)
begin: Output_Register_process
if (reset == 1'b0) begin
output_register <= 0.0000000000000000E+00;
end
else begin
if (clk_enable == 1'b1) begin
output_register <= output_typeconvert;
end
end
end // Output_Register_process
// Assignment Statements
assign filter_out2 = $realtobits(output_register);
endmodule // filter
delay_pipeline 是什么原语啊？ 哪款XILINX的FPGA支持这个？ |
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发表于 2013-12-15 07:57:49
