ESD Protection Design Methodology

rachel0131

ESD Protection Design Methodology in
Deep Sub-micron CMOS Technologies

ffqq

我正做这个课题，可是下载不了

ffqq

强烈要求下载

semico_ljj

Conclusions
ESD is a destructive phenomenon that causes reliability problems and even permanent
damage to the ICs. With the aggressive scaling of modern deep-submicron salicided CMOS
technologies, the ICs are becoming more vulnerable to ESD. To prevent the ESD related failures,
efficient on-chip protection structures are needed. However, a protection scheme that is suitable
in the present technology may not be useful for the future generations of the technology.
Therefore, a systematic approach is needed for ESD protection circuit design that can be
transferred to the future technologies. To develop an ESD design methodology, a good
understanding of the device physics under high current (electric field/temperature) conditions is
essential. In this report, we presented a complete design methodology along with some new
effects that are observed in 0.13 μm CMOS technology. We discussed the effects of bias
conditions and layout parameters on the ESD robustness of an NMOS device for both silicided
and non-silicided structures. We observed that an appropriate combination of bias conditions and
layout parameters could maximize the ESD robustness of the device. This optimization can be
achieved by developing simulation tools for ESD circuits.

semico_ljj

Circuit simulators such as SPICE have
limitations in terms of operating voltages and currents. However, device simulators such as
MEDICI can simulate the device behavior under ESD conditions. A combination of MEDICI and
SPICE can provide a very useful simulation tool. MEDICI can simulate the device-under-test
(DUT) and pass the nodal solution (voltages and currents) to SPICE, which can simulate the
complete circuit along with the voltage/current sources and other circuit elements. MEDICI
performs 2D simulation of a device, which may not be accurate enough for the future
technologies (sub-100 nm). Hence, compact models that combine 3D and thermal effects are
needed to achieve a fast and accurate simulation. Most of the device simulators available today do
not simulate the inter-finger heat transfer and hence underestimate the ESD performance of a
device. Therefore development of a simulator that incorporates inter-finger heat transfer will
improve the accuracy of the simulation. The development of mixed-signal mixed-mode
programming languages such as VHDL-AMS can play an important role in ESD protection
circuit design since VHDL-AMS can simulate the interdependence of electric field, temperature
and current using the model equations to provide a custom design environment.

semico_ljj

ESD Protection Design Methodology in Deep Sub-micron CMOS Technologies
by
Nitin Mohan Anil Kumar

Project Report
Course E&CE 730 (Topic 9)
VLSI Quality, Reliability and Yield Engineering
Winter 2003

semico_ljj

Table of Contents
1. Introduction 5
2. ESD Protection Devices 7
2.1 Resistor 7
2.2 Diode 8
2.3 NMOS Transistor 9
2.4 Silicon Controlled Rectifier 11
3. Experimental Techniques 13
3.1 Transmission Line Pulsing 13
3.2 Emission Microscopy 14
4. ESD Protection Circuit Design 15
5. Non-uniform Bipolar Conduction 21
5.1 Substrate Bias Effect 23
5.2 Gate Bias Effect 24
5.3 Effect of Gate to Contact Spacing 26
5.4 Effect of Gate Length 28
6. Simulation Methods and Applications 30
6.1 Lattice Temperature and Temperature Dependent Models 30
6.2 Curve Tracing 32
6.3 Mixed Mode Simulation 34
6.4 Extraction of MOSFET I-V Parameters 35
6.5 Simulation of Dielectric Failure 36
7. High Speed ESD Protection Scheme 38
7.1 Inductor-Based and Distributed ESD protection 38
8. Conclusions 43
9. References 44

hawk3130

都是有钱人啊 ，就俺穷：（

hawk3130

不用说下了，看都看不着

rachel0131

It is so pity that you cant download it.
If you want it for sure,you can search it from GOOGLE.I just download it from website.
Good luck!