|
|
马上注册，结交更多好友，享用更多功能，让你轻松玩转社区。
您需要 登录 才可以下载或查看，没有账号？注册
x
请问有没有Design-for-Test and Test Optimization Techniques for TSV-based 3D Stacked ICs?
谢谢!
Noia, Brandon, Chakrabarty, Krishnendu
Springer
2014, XVIII, 245 p. 133 illus., 115 illus. in color.
Provides a comprehensive guide to the challenges and solutions for the testing of TSV-based 3D stacked ICs
Includes in-depth explanation of key test and design-for-test technologies, emerging standards, and test- architecture and test-schedule optimizations
Encompasses all aspects of test as related to 3D ICs, including pre-bond and post-bond test as well as the test optimization and scheduling necessary to ensure that 3D testing remains cost-effective
This book describes innovative techniques to address the testing needs of 3D stacked integrated circuits (ICs) that utilize through-silicon-vias (TSVs) as vertical interconnects. The authors identify the key challenges facing 3D IC testing and present results that have emerged from cutting-edge research in this domain. Coverage includes topics ranging from die-level wrappers, self-test circuits, and TSV probing to test-architecture design, test scheduling, and optimization. Readers will benefit from an in-depth look at test-technology solutions that are needed to make 3D ICs a reality and commercially viable.
• Provides a comprehensive guide to the challenges and solutions for the testing of TSV-based 3D stacked ICs;
• Includes in-depth explanation of key test and design-for-test technologies, emerging standards, and test- architecture and test-schedule optimizations;
• Encompasses all aspects of test as related to 3D ICs, including pre-bond and post-bond test as well as the test optimization and scheduling necessary to ensure that 3D testing remains cost-effective. |
|
/1 
eetop公众号
创芯大讲堂
创芯人才网
发表于 2013-11-21 18:36:16
楼主
