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KT咨询-IC电子

1【猎头职位：上海需要一位“Design Engineer”】关键词：ASIC design verification,联系人：Susan，MSN:lushan630@hotmail.com；Skype:susan.lu63；Email: susan-lu@kthr.com，微信也可查询职位啦！打开手机微信，搜号码“KTHR_COM”或查找微信公众帐号“KT人才”或扫描以上二维码即可添加，欢迎大家关注！

Requirements:

·3+ years experience in ASIC design

·BS in Electrical Engineering (or equivalent) is a must have, MSEE is desired

·System on Chip (SOC) Integration Experience, including AHB/AXI, CPU, Interface integration

·Experience with WIFI or related wireless technology (i.e. WIMAX, 3G, LTE, etc.) is a plus

·Experience with interfaces such as PCIe, Ethernet, DDR, USB

·Working knowledge of networking protocols such as TCP/IP, 802.3, 802.11

·Working knowledge of C programming language

·Experience with Medium Access protocols a plus

·Must be expert in Verilog RTL language

·Must be familiar with the ASIC design flow from RTL through synthesis, including the tool flow.

·Verification experience – Verilog, System-Verilog, Coverage Analysis

·FPGA emulation experience

·Chip bring-up experience, including use of Logic Analyzer and Oscilloscope for debugging

2【猎头职位：上海需要一位“Verification Engineer”】联系人：Susan，MSN:lushan630@hotmail.com；Skype:susan.lu63；Email: susan-lu@kthr.com，微信也可查询职位啦！打开手机微信，搜号码“KTHR_COM”或查找微信公众帐号“KT人才”或扫描以上二维码即可添加，欢迎大家关注！

Requirements:

·3+ years experience in ASIC Verification

·BS in Electrical Engineering (or equivalent) is a must have, MSEE is desired

·System on Chip (SOC) Verification Experience, including AHB/AXI, CPU, Interface integration verification

·Very familiar with verification languages – Verilog, System-Verilog, and VMM

·Test plan and test case documentation

·Functional coverage and code coverage analysis

·Must be familiar with various scripting languages used in verification, including Perl, Csh, Make, etc.

·Experience verifying interfaces such as PCIe, Ethernet, DDR, USB

·Working knowledge of networking protocols 802.3 and 802.11, especially Medium Access Control and TCP/IP

·Working knowledge of C programming language

·Must be familiar with the ASIC verification flow from feature identification to test bench development and through final tape out sign-off

·FPGA emulation experience a plus

·Chip bring-up experience, including use of Logic Analyzer and Oscilloscope for debugging