Title: Principal Product Engineer—DDR IP

kengteng

Title: PrincipalProduct Engineer—DDR IP

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If you have interest, PLS send your update CV to zhangyl@cadence.com

PositionDescription:

Cadence is looking for an individual to work in anestablished memory controller design IP team. The group provides configurableDDR memory controller and PHY IP for ASICs. The job will be mainly focused onproviding technical support to customers, however there will be a variety ofother engineering tasks that will allow the candidate to expand skills andresponsibilities.

Provide technical support to customers for integration of IPinto ASICs including:

- Debugging of customers’ simulation or silicon issues.

- Reviewing of customers’ integration of our IP.

- Reviewing static timing reports to assist with customers’timing closure.

- Answering technical questions about IP operation.

- Train field engineers in IP operation.

- Interface with the R&D Team to bridge productimprovements and resolve customer issues.

PositionRequirements:         

- Excellent oral and written communication.

- BS + 5 years of prior work-experience or MS + 2 years ofprior work-experience

- All front-end skills – RTL design & verification inVerilog, synthesis, static-timing analysis, DFT

- Back-end skills – place & route, physicalverification, timing closure

- Time management skills sufficient to balance multiplehigh-priority projects.

- Willingness to learn new skills and perform tasks thatoften go outside area of current expertise.

Additional Desirable Qualifications:

- Experience with Static Timing scripts and report analysis

- Familiarity with DDR memory operation, systemapplications, AXI, OCP, AHB

- Familiarity with Framemaker

- Scripting – in Perl, TCL, etc..