Cadence NCverilog SimVision User Guide教程

gang0924

今天学习 NCSIM 谢谢

bluesmaster

`timescale1ns/1ns
module clkgen(fetch,clk2,clk,alu_clk);
output fetch,clk2,clk,alu_clk;
reg fetch,clk2,clk;
`define period 80
assign alu_clk = ( fetch | clk2 | clk );
initial
fork
clk=0;
clk2=1;
fetch=1;
forever #(`period/2) clk = ~clk;
forever #(`period) clk2 = ~clk2;
forever #(`period*2) fetch = ~fetch;
join
endmodule

gq101120055

谢楼主分享 ！！！

michael_sina

非常感谢楼主分享

欧德布莱克曼

非常感谢

yeminhua01

thank you

MSES

好东西

edward2013

谢谢分享

zengsir

谢谢楼主分享

jimcmwang

Cadence NC-Verilog Simulator Help8.2.pdf (11.12 MB)

  SimVision User Guide8.2.pdf (3.09 MB)

  Candence_NC-Verilog Simulator Tutorial.pdf (968.16 KB)

  NC-Verilog仿真详解.doc (43.5 KB)