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本帖最后由 xinlianxin 于 2013-9-25 19:01 编辑
Low Power 12-bit SAR ADC for Autonomous Wireless Sensors Network Interface
Abstract
Design strategies for power effective and high resolution successive-approximation ADCs for autonomous multi-sensor systems are discussed. Specifically, an optimisation for lowest possible power consumption of comparators is addressed and evaluated using both simulations and measurements of a fabricated Si test-chip. The proposed design solution is capable to provide a 12-bit resolution at 50-kHz with only 0.1 muW power consumption on a 1.2-V supply. The achieved Figure-of-Merit is 165 fJ/convertion-step is, to our knowledge, the best ever reported. The complete ADC area is 0.35 mm2 in NXP 0.14 mum CMOS technology with only three metal layers.
Published in:
Advances in sensors and Interfaces, 2009. IWASI 2009. 3rd International Workshop on Date of Conference: 25-26 June 2009
A 3.3 V 12 bits railto- rail ADC SAR for neuronal implant
This paper presents the development of a low-power rail-to-rail SAR-ADC to be used in a medical implants. The first part discusses the principle schematic and the requirements for the neuronal implant application. Additionally, a full description of each part of this ADC SAR will be given. And finally the last part presents measurement results of a fabricated test chip in 0.35μM CMOS technology, with 86μW of power consumption, 12bits of resolution, and a speed of 24Ks/S.
Published in:
NEWCAS Conference (NEWCAS), 2010 8th IEEE InternationalDate of Conference: 20-23 June 2010
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发表于 2013-9-25 11:34:53
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