High Performance Multi-Channel High-Speed I/O Circuits

hi_china59

High Performance Multi-Channel High-Speed I/O Circuits by Taehyoun Oh,


ISBN: 1461449626
2014



This book describes design techniques that can be used to mitigate crosstalk in high-speed I/O circuits. The focus of the book is in developing compact and low power integrated circuits for crosstalk cancellation, inter-symbol interference (ISI) mitigation and improved bit error rates (BER) at higher speeds. This book is one of the first to discuss in detail the problem of crosstalk and ISI mitigation encountered as data rates have continued beyond 10Gb/s. Readers will learn to avoid the data performance cliff, with circuits and design techniques described for novel, low power crosstalk cancellation methods that are easily combined with current ISI mitigation architectures.


Contents
1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.1 Low Impedance Microstrip-Line FEXT Model . . . . . . . . . . . . . 2
1.2 Predicting Eye-Diagram Properties from the Pulse Response . . . 3
1.3 Single-Ended Versus Differential Signaling . . . . . . . . . . . . . . . 6
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2 236 Gb/s MIMO Crosstalk Cancellation and Signal
Reutilization Scheme in 130 nm CMOS Process . . . . . . . . . . . . . . 11
2.1 MIMO-XTCR Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.2 2  2 MIMO-XTCR Prototype Implementation . . . . . . . . . . . . . 14
2.2.1 2  2 MIMO-XTCR in Single-Ended I/Os . . . . . . . . . . . 14
2.2.2 2  2 MIMO-XTCR in Differential I/Os . . . . . . . . . . . . 18
2.3 Measurement Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
2.3.1 2  2 MIMO-XTCR Gain Calibration:
Single Input Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
2.3.2 2  2 MIMO-XTCR Measurement Results:
Two Independent Input Signals. . . . . . . . . . . . . . . . . . . 21
2.4 Conclusions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
3 4312 Gb/s MIMO Crosstalk Cancellation and Signal
Reutilization Receiver in 65 nm CMOS Process . . . . . . . . . . . . . . 27
3.1 Characteristic of Far-End Crosstalk and Proposed
Channel Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
3.1.1 Factors for Crosstalk Strength. . . . . . . . . . . . . . . . . . . . 28
3.1.2 Proposed Channel Architecture for Multi-Lane
Single-Ended I/Os . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
3.2 Proposed Low Power XTCR Analog Front-End
for Multi-Lanes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
3.2.1 XTCR on Multi-Lanes (C4) . . . . . . . . . . . . . . . . . . . . . 33
3.2.2 Prototype Low Power Analog Front-End
Circuit Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
ix
3.3 Verifying Crosstalk Cancellation Using Multi-Lane Signals . . . . 39
3.3.1 XTCR Gain Calibration . . . . . . . . . . . . . . . . . . . . . . . . 39
3.3.2 Measurement Verification for Practical Application . . . . 42
3.4 Conclusions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
4 Adaptive XTCR, AGC, and Adaptive DFE Loop. . . . . . . . . . . . . . 47
4.1 Understanding Crosstalk Behavior . . . . . . . . . . . . . . . . . . . . . . 49
4.2 Adaptive XTC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
4.3 Automatic Gain Control and Adaptive Decision
Feedback Equalization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
4.4 Combining the Adaptation of the XTC, AGC
and DFE Coefficients. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
4.5 Conclusions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
5 Research Summary and Contributions . . . . . . . . . . . . . . . . . . . . . 69
Appendix A: Noise Analysis. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
Appendix B: Issues of Applying Consecutive 232 XTCR
on Multi-Lane I/Os (‡4) . . . . . . . . . . . . . . . . . . . . . . . . 77
Appendix C: Transmitter-Side Discrete-Time FIR XTC Filter
Versus Receiver-Side Analog-IIR XTC Filter . . . . . . . . . 79
Appendix D: Line Mismatch Sensitivity . . . . . . . . . . . . . . . . . . . . . . . 83
Appendix E: Input Matching for 434 XTCR Receiver
Test Bench . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
Appendix F: Bandwidth Improvement by Technology Scaling. . . . . . . 87
x Contents

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