[猎头]资深数字前端/后端设计&前端验证工程师

bestgrace

招聘资深数字前端/后端设计&前端验证工程师

Ifyou have interest, PLS send your update CV to bestgrace@qq.com  
Title: Principal/Lead Front-end Design Engineer

  

PositionDescription:

Deliver/implement IP design. The engineer shouldbe able to act as a strong team member and contributor.

Specific duties include:

- Proficiency in logic design, simulation,synthesis, STA and testing

- Proficiency in Verilog and its simulationenvironment

At least five years experience driving complexIC development projects, excellent communication skills and the uncanny abilityto both lead and contribute in a cooperative team environment is required.

  

PositionRequirements:

1.BS degree with 6~10+ years of applicableexperience, MS degree with 4~7+ years of applicable experience in electricalengineering, microelectronics, comparable engineering science or solid statephysics.

2.Essential that the individual demonstratesstrong communication, verbal and written. 3.Requires good communication skillsin English.



  

Title：PrincipalPhysical design Engineer



Position Description:

Thecandidates should be senior in a way that they are not only technical excellentbut also mature & able to communicate with customers, following teammembers. This engineer should have excellent design experiences in the digitalimplementation domain including Floorplan, P&R, STA, Physical verification,DFM. The engineer must have a solid background in circuits, electronics &physics & should be very willing to learn new stuff.

1. Abilityto handle large sized design implementation tasks & architectural tasksalone.

2. Abilityto assess Customer's Design environment, to understand his application needs& to build new Design environment based on specifications & availableCadence tool technology.

3. Abilityto acquire a basic understanding of the (services) business environment ofCadence within 1 month. Working on multi person projects of varying complexity,working especially in a multi-site/multi-cultural project.

4. Goodcommunication skills in English. Feel responsible for technical delivery aswell as business development & opportunity creation.

5. Behavioralcompetencies: Teamwork; Customer focus; Accountability; Communication; Coaching& feedback; Employee development; Leadership.



Position Requirements:

1. Musthave BS degree with 15+ years of applicable experience, MS degree with 10+years of applicable experience in electrical engineering, microelectronics.

2. Essentialthat the individual demonstrates strong communication, verbal and written, andproject management skills.

3. Requiresgood communication skills in English.



  

  

Title：Principal Verification Engineer

  



Position Description:

Deliver/implementadvanced verification solutions by utilizing Cadence’s Incisive Verificationproduct portfolio. The engineer should be able to act as a strong team memberand contributor, leading team projects and initiatives. Exercise judgmentwithin generally defined practices and policies.

Specific duties include:

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Deep understanding on ASIC/SOCdesign flow

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Excellent knowledge of advancedverification methodology like eRM/OVM/UVM

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Familiar with Cadence’s IncisivePlan to Closure Methodology (IPCM)

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Proficiency in SystemVerilog, System C and/or e (Specman)

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Developing and using VerificationComponents (eVC, OVC, UVC, VIP)

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Developing and using assertionbased verification and formal analysis methods

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Skilled in scripting language,such as Perl, C shell, Makefile

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Assessing the projectverification requirements

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Operating in a lead roleregarding architecting and implementation of project verificationenvironment/solution.

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May coordinate/lead others withinthe scope of a defined project

  

Position Requirements:

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Have BS degree with 7~10 years ofapplicable experience, MS degree with 4~7 years of applicable experience inelectrical engineering, microelectronics, comparable engineering science orsolid state physics.

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Requires good communicationskills in English.

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A minimum of seven years relevantexperience in industry.

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Will have demonstrated hands-onexperience and expertise with Cadence verification design tools or equivalenttools, flows and methodologies required to execute a verification project.

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Will have demonstrated successfulcompletion of 10+ verification projects as an individual contributor



E-Mail: bestgrace@qq.com

QQ: 2043753191

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