【猎头急招】ASIC Design/Verification Engineer

bestgrace

ASIC Design/Verification Engineer



RESPONSIBILITIES:

- RTL design, verification, synthesis for various low power control logic in GPU chips.

- Develop and maintain verification environment at both full chip & unit level

- Code/functional coverage analysis

- Responsible for running both RTL & gate level simulation

- Develop testing and regression methodologies

- Develop/maintain/enhance environment tools/scripts/makefiles



MINIMUM REQUIREMENTS:

- BSEE/MSEE/BSCS/MSCS with 3+/5+ years of experience in ASIC design or verification

- Proficient in Verilog HDL

- Familiar with logic simulators and debug tools (VCS, NCSIM, Verdi and etc.)

- Working knowledge in C/C++, Makefile

- Must have strong programming skills in one or more scripting languages: TCL, Perl, Python

- Knowledge in one of the below areas is a big plus

+ UVM/VMM experience

+ Low power design/verification experience (Multi-Voltage, power gating, UPF/APF and etc.)

+ ARM based SoC verification experience

+ AHB/AXI architecture

+ Embedded OS







E-Mail: bestgrace@qq.com

QQ: 710065861

新浪blog:
http://blog.sina.com.cn/u/1767088102

新浪微博:
http://weibo.com/bestgrace



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duanli112

shanghai?

wobushi

同问，看了bestgrace的几个帖子，都没写工作地点。