interlaken 以太网 路由器 asic系列

jj_seu

FPGA高级设计工程师

职责描述：

1. 与市场和软件人员合作，参与评估客户需求和制定网络数据包处理板卡的设计方案

2.
负责FPGA的Specification和设计实现

3.
负责板卡的系统验证和联调，协助客户进行测试

职位要求：

1.
有设计用于Ethernet/IP数据包处理的FPGA的工作经验

2.
具有调试由FPGA、CPU 和ASIC组成的板卡的经验和能力。

3.
熟悉PCIe等接口设计

4.
良好的团队合作和敬业精神

5.
有数据网络通信系统设计经验者优先

高级软件工程师

职位描述：

1.    SP(SearchProcessor)的SDK开发，提供SP所实现的各项功能。

2.    理解客户系统中SP的应用和技术要求，设计符合市场需求的API。

3.    为客户提供SP应用相关的技术方案。

职位要求：

1.    能够独立完成SDK和API设计开发工作。

2.    有SDK开发经验，具有开发和优化算法的能力。

3.    熟悉硬件，有linux或者VxWorks底层驱动程序开发经验。

4.    良好的语言沟通能力。

5.    良好的团队合作精神和敬业精神

6.    有路由器、交换机经验，熟悉转发流程和相应的软件，特别是与查找相关的算法和软件经验是big plus。

7.    有TCAM使用方面的工作经验者佳

IC Design Leader/Manager：

Responsibilities:
1.Lead other Design Engineers in a team to meet thecompany's objectives；

2. Design and implement digital communicationsystem blocks and whole chip including specification trade-offs andoptimization, micro-architecture, RTL coding, Synthesis, STA and simulation,chip testing and characterization.

3.This is a full-time position with solid equityopportunity.

Requirements:
1.5+ years of experience in Verilog/Synthesis-based ASIC Design for massproduction IC chipsExperience with project and team management
2.Experience from front-end to back-end (RTL, synthesis, verification, and testsupport) with data networking ASIC(Ethernet, TCP/IP)
3.Verilog language and simulation verification experience
4.Logic Synthesis and Static Timing Analysis
5.Interface with Place and Route and back-annotated simulation verification
6.Team-work spirit, and with a strong drive to excel

IC Design
Engineer：

Responsibilities:
1.Work with other Design Engineers to meet the company's objectives；

2.Design and implement digital communication systemblocks and whole chip including specification trade-offs and optimization,micro-architecture, RTL coding, Synthesis, simulation and verification, chiptesting and characterization.

3.This is a full-time position with solid equityopportunity.
Requirements:
1.3+ years of experience in Verilog/Synthesis-based ASIC Design
2.Experience with front to back (RTL, synthesis, verification, and testsupport) with data networking ASIC(Ethernet, TCP/IP)
3.Verilog language and simulation verification experience
4.Logic Synthesis and Static Timing Analysis
5.Interface with Place and Route and back-annotated simulation verification
6.Team-work spirit, and with a strong drive to excel

IC Verification Senior Engineer/Lead：

Responsibilities:
1.Compose the verification plan according to the chip specification andcustomer's use cases;
2.Adopt the advanced verification methodologies to create the wholeverification environment from scratch according to the requirements of specificIC;

3.Design Behavioral functional model and test-benches with C/System C,Verilog/System Verilog and script languages
4.Create, build and implement test cases with high degree of accuracy to verifyDevice Under Test
5.Work closely with concept architect and RTL designer to verify RTL designthrough extensive test-bench simulation for modular and top-level design toobtain very high percentage of functional and code coverage

6.Work closely with FPGA prototyping application and validation engineers toverify functional design
7.Coach the inexperienced engineers in the team
8.Secondary task may include design of digital logic with high-leveldescription language (VHDL/Verilog) from specification.
Requirements:
1.Master's/Bachelor's Degree in Electrical/Electronics or Computer Engineering.
2.5+ years IC verification experience on the complex ASIC/SOC
3.Experience with advanced verification methodologies(VMM, OVM, UVM, etc.) including functionalcoverage and constrained random testing

4.Good knowledge of C, SystemC, and at least one of script languages: Perl,Python, etc.
5.Expert knowledge of VHDL/Verilog HDL and CAD tools (Synopsys and/or Cadence)
6.Team-work spirit, and with a strong drive to excel
7.Able to work independently on a given assignment and work hard to finish ontime
8.Good written and communication skills
9.Previous experience on data network communication IC is an added advantage

IC Verification Engineer：

Responsibilities:
1.Compose the pre-silicon verification plan according to the chip specificationand customer's use cases
2.Design Behavioral functional model and test-benches with C/System C. HDL andscript languages
3.Create. build and implement test cases with high degree of accuracy to verifyDevice Under Test
4.Work closely with concept architect and RTL designer to verify RTL designthrough extensive testbench simulation for modular and top-level design toobtain very high percentage of functional and code coverage
5.Work closely with FPGA prototyping application and validation engineers toverify functional design
6.Coach the inexperienced interns in the team
7.Secondary task may include design of digital logic with high-leveldescription language (VHDL/Verilog) from specification.

Requirements:

1,Master's/Bachelor's Degreein Electrical/Electronics or Computer Engineering.
2,Experience with verification methodologies including functional coverage andconstrained random testing
3,Good knowledge of C, SystemC, and at least one of script languages: Perl,Python, etc.
4,Expert knowledge of VHDL/Verilog HDL and CAD tools (Synopsys and/or Cadence)
5,Team-work spirit, and with a strong drive to excel
6,Able to work independently on a given assignment and work hard to finish ontime
7,Good written and communication skills
8,Previous experience in data communication network IC area is an addedadvantage

贵司有招聘需求的，欢迎和我联系；

如果你和你朋友有需要看工作机会的，发简历给我Jane-Jin@Hi-Talent.net

Best Regards,

Jane.Jin

Principal Consultant & General Manager @ Hi-TalentConsulting Co.,Ltd.

上海芯相会企业管理咨询有限公司

Skype:      ScarlettJaneJin

E-Mail:      Jane-Jin@Hi-Talent.net

QQ:         1687562641

Blog:        http://blog.sina.com.cn/u/1716864892

Weibo:      http://weibo.com/u/1716864892

Linkedin:    jj_seu@hotmail.com

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