Cadence Allegro SPB 16.6 Hotfix S013

scottt

DATE: 07-26-2013   HOTFIX VERSION: 013  ============1/55 to 20/55==================================================================
CCRID   PRODUCT        PRODUCTLEVEL2   TITLE
===================================================================================================================================
111368  CAPTURE        CORRUPT_DESIGN   Capture - will not produce allegro netlist with 10.0
134439  PD-COMPILE     USERDATA         caCell terminals should be top-level terminals
186074  CIS            EXPLORER         refresh symbols from lib requires you to close CIS
583221  CAPTURE        SCHEMATIC_EDITOR Option to have the Schematic Page Name as a Property in the Titleblock
591140  CONCEPT_hdl    OTHER            Scale overall output size in PublishPDF from command line
801901  CONCEPT_HDL    CORE             Concept Menus use the same key "R" for the Wire and RF-PCB menus
813614  APD            DRC_CONSTRAINTS  With Fillets present the "cline to shape" spacing is wrong.
881796  ALLEGRO_EDITOR GRAPHICS         Enhancement request for Panning with Middle Mouse Button
887191  CONCEPT_HDL    CORE             Cannot add/edit the locked property
911292  CONCEPT_HDL    CORE             Property command on editing symbol attaches property to ORIGIN immediately
987766  APD            SHAPE            Void all command gets result as no voids being generated on specific env.
1001395 SIP_layout     ASSY_RULE_CHECK  Shape Minimum void check reports lots of DRCs which are not necessary to check out.
1030696 ALLEGRO_EDITOR INTERACTIV       Enh - Allow another behavior of PAN movement using middle mouse in Allegro
1043856 ADW            TDA              Diff between TDO and DE-HDL Hierarchy Viewer is confusing to the user
1046440 ADW            PCBCACHE         ADW: ImportSheet is not caching libraries under flatlib/model_sym when the source design is not an ADW project
1077552 F2B            PACKAGERXL       Diff Pairs get removed when packing with backannotation turned on
1079538 F2B            PACKAGERXL       Ability to block all 窺ingle noded nets?to the board while packaging.
1086362 ALLEGRO_EDITOR SHAPE            Enhancement request to autovoid a via if shape cannot cover the center of the via.
1087958 PSPICE         MODELEDITOR      Is there any limitation for pin name definition?
1087967 CIS            UPDATE_PART_STAT Update part status window shows incorrect differences
1090693 ADW            LRM              LRM auto_load_instances does not gray out Load instances Button
1097246 CONCEPT_HDL    CORE             ConceptHDL - assign hotkeys to alpha-numerical keys
1099773 CONCEPT_HDL    CORE             DE HDL goes into recursive loop if a custom text locked at site level is deleted from Tools > Option
1100945 SCM            SCHGEN           SCM generated DE-HDL has $PN placement issue
1100951 PSPICE         SIMULATOR        Increasing the resolution of fourier transform results in out file
1103117 RF_PCB         FE_IFF_IMPORT    Enh- Allow the Allegro_Discrete_Library_to_ADS_Library_Translator to output in its original unit
1105473 PSPICE         PROBE            Getting error messages while running bias point analysis.
1106116 FLOWS          PROJMGR          view_pcb setting change was cleared by switching Flows in projmgr.
1106298 ALLEGRO_EDITOR INTERACTIV       Copy Shape uses last menu pick location as origin and not the Symbol Origin as specified in Options.
1106626 CONCEPT_HDL    CORE             Concept HDL crashes when saving pages
1107086 ALLEGRO_EDITOR INTERACTIV       manual void with arc's goes in wrong direction during arc creation
1107172 CONCEPT_HDL    OTHER            Project Manager Packager does not report errors on missing symbol
1108193 CONCEPT_HDL    CORE             Using the left/right keys do not move the cursor within the text you're editing
1108603 PCB_LIBRARIAN  VERIFICATION     PDV Tools Verification > View Verification (CheckPlus) leaves <project>.cpm_tmp.cpm
1109024 CIS            OTHER            OrCad performance issue from Asus.
1109109 CAPTURE        NETLIST_ALLEGRO  B1: Netlist missing pins when Pack_short property pins connected
1109466 ALLEGRO_EDITOR ARTWORK          Artwork create some strange gerber lines for fillet.
1109647 SIP_LAYOUT     DEGASSING        Shape degassing command enhancement - control over what layers are counted in even/odd layer sets.
1109926 CONCEPT_HDL    CORE             viewing a design disables console window
1110194 SIP_LAYOUT     WIREBOND         If OpenGL settings for display of dynamic net names is enabled, should be visible while push/shove wirebonds.
1112357 SIP_LAYOUT     WIREBOND         wirebond command crashes the application
1112395 CONCEPT_HDL    CORE             璞BASE\G?for global signal is not obeyed after upreving the design to 1650.
1112658 CAPTURE        PROPERTY_EDITOR  Changing Part 澶raphic?value from property Editor Changes Occ refdes values to instance
1112662 CAPTURE        PROJECT_MANAGER  Capture crashes after moving the library file and then doing Edit> Cut
1113177 PCB_LIBRARIAN  CORE             Pin Shapes are not getting imported properly
1113380 ALLEGRO_EDITOR INTERACTIV       Change layer to - option for package type .dra is not available in 16.6 release
1113656 SIP_LAYOUT     WIREBOND         Enable Change characteristic to work without unfixing its Tack point.
1113838 SIP_LAYOUT     DIE_ABSTRACT_IF  probe pins defined in XDA die abstract file are added with wrong location
1113991 CAPTURE        GENERAL          Save Project As is not working if destination is a linux machine
1114073 APD            DRC_CONSTRAINTS  Shape voiding differently if there are Fillets present in the design.
1114241 CAPTURE        SCHEMATIC_EDITOR Port not retaining assigned color, when moved on the schematic
1114442 PSPICE         PROBE            Getting Internal error - Overflow Convert with marching waveform on
1114630 CONCEPT_HDL    ARCHIVER         Archcore fails because the project directory on Linux has a space in the name
1114689 CONCEPT_HDL    CORE             Unknown project directive : text_editor
1114928 F2B            PACKAGERXL       激rror (SPCODD - 5) while Export Physical even after change pin from A<0> to A
1116886 CONCEPT_HDL    CORE             Crefer hyperlinks do not work fine when user use double digits partitions for page Border.
1118088 ALLEGRO_EDITOR EDIT_ETCH        Should Plan accurate and Optimize be removed in 16.6?
1118734 APD            EDIT_ETCH        Multiline routing with Clines on Null Net cannot route in downward direction
1118756 ALLEGRO_EDITOR SHAPE            Shape clearance parameter oversize values getting applied to Keepouts
1119606 CONCEPT_HDL    MARKERS          Filtering two or more words in Filter dialog box
1119707 CONCEPT_HDL    CORE             Genview does not use site colors when gen sch from block symbol
1119711 F2B            DESIGNSYNC       Design Differences show Net Differences wrongly
1120659 CAPTURE        PROJECT_MANAGER  "Save project as" does not support some of Nordic characters.
1120660 CONCEPT_HDL    CORE             Save hierarchy saves pages for deleted blocks.
1120817 SIP_LAYOUT     SYMB_EDIT_APPMOD Rotate Pads commands not working while in the Symbol Edit App. mode
1120985 PSPICE         MODELEDITOR      Unable to import attached IBIS model
1121171 CONCEPT_HDL    CREFER           PNN and correct property values not annotated on the Cref flat schematic
1121353 ALLEGRO_EDITOR INTERACTIV       Local env setting will change after saving and reopening.
1121382 ALLEGRO_EDITOR INTERACTIV       Undo command is limited to two for this design
1121540 F2B            PACKAGERXL       pxl.chg keeps deleting and adding changes on subsequent packager runs
1121558 ALLEGRO_EDITOR MODULES          Unrouted net and unrouted connection when module is placed of completely routed board file.
1121585 ALLEGRO_EDITOR OTHER            Drill Hole to Shape Same Net Spacing with Dynamic Shapes shows wrong result.
1121651 CAPTURE        SCHEMATIC_EDITOR "PCB editor select" menu option is missing
1122136 SIP_LAYOUT     PLACEMENT        Moving a component results in the components outline going to bottom side of the design.
1122340 CAPTURE        NETLIST_ALLEGRO  Cross probe of net within a bus makes Capture to hang.
1122489 CONCEPT_HDL    OTHER            Save _Hierarchy causing baseline to brd files
1122781 CONCEPT_HDL    CORE             cfg_package is generated for component cell automatically
1122909 CONCEPT_HDL    CORE             changing version replicates data of first TOC on 2nd one
1123150 CONCEPT_HDL    CORE             property on y axis in symbol view was moved by visibility change to None.
1123176 ALLEGRO_EDITOR UI_FORMS         Negative values for pop-up location is not retained with multiple monitors (more than 2)
1123815 ALLEGRO_EDITOR GRAPHICS         Embedded netname changes to a different netname
1124369 ALLEGRO_EDITOR INTERACTIV       Sliding a shape using iy coordinate does not work indepedent of grid.
1124544 CONCEPT_HDL    CORE             About Search History of find with SPB16.5
1124570 APD            IMPORT_DATA      When importing Stream adding the option to change the point
1125201 CONCEPT_HDL    CORE             Connectivity edits in NEW block not saved( lost) if block is created using block add
1125314 ALLEGRO_EDITOR INTERACTIV       Enved crash during setting of library paths in user preference
1125366 CONCEPT_HDL    CORE             DE-HDL craches during Import Physical if CM is open on Linux
1125628 CONCEPT_HDL    CORE             Crash on doing save hierarchy
1130555 APD            WIREBOND         Wirebond Import should connect to pins of the die specified on the UI.
1131030 PSPICE         ENVIRONMENT      Unregistered icon of Simulation setting in taskbar
1131083 ALLEGRO_EDITOR INTERACTIV       Bug: 16.6 crash in changing the mode in Find filter window
1131226 ALLEGRO_EDITOR PLACEMENT        When Angle is set in design parameters while placement component is rotated but outline is not.
1131567 CONCEPT_HDL    OTHER            Lower case values for VHDL_MODE make genview use pin location to determen direction.
1131699 PSPICE         PROBE            Probe window crash on trying to view simulation message
1132457 CONCEPT_HDL    CORE             The schematic never fully invokes and has connectivity errors.
1132575 CONCEPT_HDL    CORE             2 pin_name were displayed and overlapped by spin command.
1132698 ALLEGRO_EDITOR EDIT_ETCH        Slide Via with Segment option with new Slide command
1132964 ALLEGRO_EDITOR SHAPE            Same net "B&B via to shape" errors created when adding shape
1133677 CONCEPT_HDL    CORE             Cant delete nor reset LOCATION prop in context of top
1133791 CONCEPT_HDL    CORE             Cant do text justification on a single selected NOTE in Windows mode.
1134761 CONCEPT_HDL    CORE             Why does Mouse Pointer/Tooltip display LOCATION instead of $LOCATION property
1135118 ALLEGRO_EDITOR INTERACTIV       Mirror and other editing commands are missing for testpoint label text in general edit mode.
1136420 CAPTURE        GENERAL          Registration issue when CDSROOT has a space in its path
1136808 PSPICE         STABILITY        Pspice crash marker server has quite unexpectedly
1136840 CAPTURE        SCHEMATICS       Enh: Alignment of text placed on schematic page
1138586 ADW            MIGRATION        design migration does not create complete ptf file for hierarchical designs
1139376 CONCEPT_HDL    CORE             setting wire color to default creates new wire with higher thickness
1140819 APD            GRAPHICS         Bbvia does not retain temp highlight color on all layers when selected.
1141300 CONCEPT_HDL    CORE             DE HDL hier_write save hierarchy log reports summarizes Successfully saved block x while block was skipped
1141723 ADW            PURGE            purge command crashes with an MFC application failure message
1143448 CAPTURE        GENERAL          About copy & paste to Powerpoint from CIS
1143670 SIP_LAYOUT     OTHER            Cross Probing between SiP and DEHDL not working in 16.6 release
1143902 ALLEGRO_EDITOR DATABASE         when the shape is rotated 45 degrees the void is moved.
1144990 PCB_LIBRARIAN  CORE             PDV expand & collapse vector pins resizes symbol outline to maximum height
1145112 CONCEPT_HDL    CORE             Warning message: Connectivity MIGHT have changed
1145253 CONCEPT_HDL    CORE             Component Browser adds properties in upper case
1146386 ALLEGRO_EDITOR INTERACTIV       Place Replicate Create add Static shape with Fillet shape
1146728 F2B            PACKAGERXL       DCF with upper and lower case values on parts causes pxl to fail
1146783 ALLEGRO_EDITOR INTERFACES       Highlighted component is missing from exported IPF file.
1147326 CONCEPT_HDL    CORE             HDL crashes when trying to reimport a block
1148337 CAPTURE        ANNOTATE         Checking "refdes control" is not giving the proper annotation result
1148633 SIP_LAYOUT     INTERACTIVE      Add "%" to the optical shrink option in the co-design die and compose symbol placement forms
1149778 CAPTURE        SCHEMATICS       Rotation of pspice marker before placement is not appropriate
1149987 PCB_LIBRARIAN  PTF_EDITOR       Save As pushing the part name suffix into vendor_part_number value
1151748 ALLEGRO_EDITOR OTHER            If the pad and cline are the same width don't report a missing Dynamic  Fillet.
1152206 CONCEPT_HDL    CORE             ROOM Property value changes when saving another Page
1152755 CONCEPT_HDL    COPY_PROJECT     Copy project hangs if library or design name has an underscore
1152769 PSPICE         ENCRYPTION       Unable to simulate Encrypted Models in 16.6
1153308 ALLEGRO_EDITOR DRC_CONSTR       Creating Artwork Getting Warning "DRC is out of Date" even when DRC is up to date
1153893 F2B            DESIGNVARI       16.6 Variant Editor not supporting - in name
1154185 SIG_INTEGRITY  SIGNOISE         Signoise didn't do the Rise edge time adjustment.
1154860 ALLEGRO_EDITOR MANUFACT         Double digit drill character overlaps with figures triangle, hexagon and octagon in NC drill legend
1155167 ALLEGRO_EDITOR EDIT_ETCH        Via structure placed in Create Fanout has incorrect rotation.
1155728 CONCEPT_HDL    CORE             Unable to uprev packaged 16.3 design in 16.5 due to memory
1155855 SCM            SCHGEN           A newly user-defined net property is not transferred from SCM to DEHDL in Preserved Mode
1156274 ALLEGRO_EDITOR INTERFACES       Exported Step file from Allegro is wrong
1156316 CONSTRAINT_MGR OTHER            Break in functionality while creation of pin-pairs under Xnet in Constraint Manager
1156351 CONCEPT_HDL    CONSTRAINT_MGR   Loose members in Physical Net Class between DEHDL and Allegro
1156547 ALLEGRO_EDITOR DRC_CONSTR       Etch Turn under SMD pin rule check through pin Etch makes confused.
1156779 CONSTRAINT_MGR OTHER            Electrical Cset References in CM not working correctly
1157167 ALLEGRO_EDITOR SKILL            axlPolyFromDB with ?line2poly is broken
1158042 ALLEGRO_EDITOR DFA              DFA_DLG writes the dra file name in uppercase.
1158718 CONCEPT_HDL    CHECKPLUS        Customer could not get $PN property values on logical rule of CheckPlus16.6.
1158970 ALLEGRO_EDITOR SCHEM_FTB        Changing LOCATION to $LOCATION in DEHDL does not update the .brd file
1158989 ALLEGRO_EDITOR INTERFACES       pdf_out -l creates a PDF
1159285 APD            DXF_IF           DXF_OUT fails; some figures are not exported
1159432 ALLEGRO_EDITOR SHOW_ELEM        http:// in the Show Element in 166 do not have HTML link to open the Website
1159483 PCB_LIBRARIAN  SETUP            part developer crashing with
1159516 ALLEGRO_EDITOR EDIT_ETCH        Unable to slide cline segment with new slide.
1159959 ALLEGRO_EDITOR GRAPHICS         3D viewer displays clines arcs incorrectly
1160004 SCM            UI               The RMB->Paste does not insert signal names.
1160410 ALLEGRO_EDITOR DATABASE         Lock databse with View Lock option is misleading
1160529 SCM            SCHGEN           Schematic generation stopped because the tool was unable to create an appropriate internal symbol structure
1160537 SPIF           OTHER            Cannot start PCB Router
1161363 ALLEGRO_EDITOR SYMBOL           Getting error SPMHGE-73 when trying to mirror symbol
1161781 CONSTRAINT_MGR CONCEPT_HDL      SigXp crash when selecting ECset in design
1161896 ALLEGRO_EDITOR DRAFTING         Tolerance value added for Dimensions is not working correctly (HF11-12)
1162193 SIP_LAYOUT     DIE_ABSTRACT_IF  shapes in dia file not linked to the die after edit co-design die
1162754 APD            VIA_STRUCTURE    Replace Via Structure command selecting dummy nets.

scottt

21-55 ----->>>> End

stroelec

看着干着急，没钱。

stroelec

无事在网上到处逛，发现了一个，下了后貌似补上去鸟！

Apiary

安装了原来的破解还能用么？

scottt

安装了cadence软件之后，已经破解好了的童鞋往下看：
1、首先把spb_16.6文件夹命名为spb_16.6old（反正和spb_16.6不一样就行了）。
2、在cadence目录里面建立一个新的空文件夹命名为spb_16.6，并把spb_16.6old的compnts.dat拷贝到空的spb_16.6中
3、安装HOTFIX补丁到空的spb_16.6中；
4、复制ToolsPubkey.bat pubkey1.30.exe pubkey 三个文件到spb_16.6\tools中并运行ToolsPubkey.bat
5、把spb_16.6里面的文件全部复制到spb_16.6old替换旧文件
6、删除spb_16.6文件夹并把spb_16.6old改回spb_16.6
你可以正常使用了

songhf601

楼主，下载完成后点击setup,提示：SPB 16.6 base release not found.无法继续安装，请问如何解决。谢谢！

scottt

請依照#6步驟,驗證ok.

yogi_yi

MARK  没钱干着急

小样儿

要全部下载吗  为什么这么多啊