[全职]AMD上海职位热招

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AMD上海研发中心热招以下职位，请感兴趣的候选人务必以“所应聘职位_姓名_学历现公司名称_工作年限” 为标题，把简历以附件形式发送到maggie1.zhang@amd.com ,请在正文称述应聘理由与优势。
1. Sr. Manager for Display –IPE MM
2.ASIC Design Engineer  Senior/MTS(FCH/NBIO/GPU/ Verification methodology/Multi-Media/display)
3.ASIC Design Verification Senior/MTS(FCH/NBIO/Graphics hardware)
4.Front-end/Back-End ASIC design CAD engineer
5.Windows/Linux 2D/3D graphics driver Senior/MTS
6.Device Driver Development Engineer(X86)
7.MTS/SE for Camera/ISP SW Development (Android)
8.OpenGL/OpenCL/Computing SW Engineer/MTS
9.Principle/Senior Staff Design Lead for 10G+ Ethernet IP
1.**Sr. Manager for Display –IPE MM
PREFERRED EXPERIENCE:
Master or PhD in Electrical Engineering or Computer Science.
10+ years of relevant experiences in related industry
In management position with global company and leading a team with 20+ engineers for 5+ years with Multi-site experience
Excellent English communication skills in both speaking and written.
Strong knowledge with C/C++, Verilog, Synthesis, Timing, Physical Design process
Strong experience of display specific-interconnection protocols (DisplayPort, HDMI, LVDS, VGA, DVI, etc) or Display process
Plus on Graphic or real time display related knowledge
Team player with open mind
2.**ASIC Design Engineer  Senior/MTS(FCH/NBIO/GPU/ Verification methodology/Multi-Media/display)
**Sr. ASIC Design Engineer   -           Display
DESCRIPTION OF DUTIES IN ADDITION TO THOSE IN JOB DESCRIPTION:
- Responsible for display IP development and maintenance
- Responsible for IP level synthesis/CDC/LEC/LINT check
- Work with verification engineer on IP verification
- Work with front-end integration team and physical design team on timing closure
- Communication with driver team to build driver
PREFERRED EXPERIENCE:
- Bachelor with 5+ yeas and Master with 3+ in Electrical or Computer Engineering.
- Strong RTL coding and familiar with front-end design flow
- Experience on synthesis, timing analysis and formal verification.
- Experience of display specific-interconnection protocols (DisplayPort, LVDS, VGA,HDCP, DVI, HDMI etc) is a plus.
- Design for verification (assertion based design strategies, code coverage, functional
coverage, test plan etc.)
- Good communication skills and fluent English.
- Strong responsibilities and team spirit.
**Member of technical staff for IC design engineering (MTS DE)
Requirements:
The candidate is preferred to be MSEE with minimum of 6 years, or BSEE with minimum of 8 years experience in digital ASIC/SOC design engineering.  
It is a must that the candidate has one or more of the following experience/knowledge, such as X86/ARM/8051 architecture, AMBA(AXI/AHB/APB) bus, USB(3.0/2.0/1.1; SSIC/HSIC/host/device/OTG) system, NAND Flash host controller/BCH/double-data-rate interface,  Universal Flash Storage, PCI-E/PCI bus, low power design, clock generation and control, SD/eMMC host controller, SATA/SAS, Legacy IPs (SPI/SMBUS/ACPI/LPC/GPIO), General connectivity IPs (I2S/I2C/UART), Ethernet, JTAG, etc.
The candidate is expected to exhibit good verbal and written communication skills in both Chinese and English, specialized knowledge plus broad technical knowledge that facilitates integrative thinking, , driving execution of quality and timely result, capability  to solve complex, novel and no-recurring problems and decision-making on critical technical areas
Responsibility:
The successful candidate will work with team members and apply his/her design techniques to work on different phases of complex logic design for ASIC/SOC project. The role will include technical leading on the following tasks from time to time: specification, top level SOC design tasks, HDL coding, etc.
**Sr. ASIC/ Layout Design Engineer (Verification CAD)
Key Job Functions:
Understand the ASIC design/verification flow and help design/verification engineers to accomplish targets.
Develop infrastructure and environment for SOC/IP level chip design verification.
Closely working with Design/Architecture/Verification team to develop new verification flow.
Preferred Experience:
Major in EE, CS or related, Master Degree with 3+ years or Bachelor with 5+ years working experiences
Familiar with Linux Environment (including command shell scripting)
Skillful at script language like ruby, perl, or tcl
Be good at C/C++ programming
Should be versatile in any one of the high level verification flow such as SV,VMM,VERA,OVM etc as well as knowledge of industry standard tools for verification
Should have excellent communication skills (both written and oral)
Strong problem solving skills
Good knowledge on verification methodology
**Staff Design/Integration Engineer for Next Generation Interconnect IP
Participate IP and SoC level architecture definition, derive functional and design specifications and analyze feasibility of technical and architectures.
Implement design with Verilog to achieve specification goals. Simulate and debug the codes in coding stage.
Go through the FE design flow to deliver qualified netlist. Feedback to Physical Design team to help to close timing and check floorplan.
Support FW/SW bring-up and debugging
Working as the technical point of contact on the ASIC area.
Maintain design environment, solve flow issues, and develop scripts to improve flow efficiency.
Essential Functions:
RTL, Synthesis, STA, Timing Analysis, Constraints
Essential Requirements/Qualifications:
Proven ASIC / SoC Design / Integration Experience
Must have strong background on IP development
Desired:
Major in EE & CS
Must be proficient in Verilog coding, debugging and modeling
should be familiar with Advanced C++/SystemVerilog, RTL coding techniques.
PCIe, Cache Management, MC, USB, BIOS, ACPI experience would be an asset.
Must be familiar with ASIC design flow, such as synthesis, DFT, timing analysis, ECO etc
Must be familiar with shell/perl/tcl programming in linux OS.
Should have strong problem solving skills
Good English hearing, speaking, reading and writing capabilities
Good communication skills
Have mass production tape‐out experience
3.** Design Verification MTS for Graphics Hardware
Position Summary
In this key role, the candidate will be responsible for low power implementation and verification of hardware.
Essential Functions
Development of infrastructure for verification of hardware in GFX IP.
Develop verification environments for feature verification, and use the automated regression infrastructure setup for IP level and IP on SoC level functional verification.
Low power design and verification for specific hardware functionality in Front-end.
Improve the low power IP delivery for variant SoCs
Requirements/Qualifications:
BS, MS or PhD in Electrical Engineering or Computer Science.
6+ years of ASIC verification or low power design experience
Should have good understanding of Pre-Silicon design process from Architecture, Design, Synthesis and Gate level Implementation till Tapeout release.
Advanced programming knowledge on Verilog/SystemVerilog, C/C++
Requires demonstrated technical expertise in the areas of Design Verification and low power design/verification methodology.
Knowledge on Perforce, OVL, SVA, SV, UVM, script programming etc.
Should have excellent communication skills (both written and oral) and should be able to participate cross functional engineering teams geographically.
Demonstrates leadership ability preferred.
Skills/Competencies:
Good design verification experience
Good communication
Strong problem solving skills
Low power design verification or computer graphics knowledge are plus
Desired:
Team Lead experience
Design Verification experience

**Member of technical staff for IC design verification (MTS DV)
Requirements:
The candidate is preferred to be MSEE with minimum of 6 years, or BSEE with minimum of 8 years experience in digital ASIC/SOC design verification.  
The candidate must have:
deep understanding on ASIC/SOC design flow
Excellent knowledge of design verification methodology, such as VMM or OVM and UVM.
Solid experiences with simulation model creation and the testbench build
Strong RTL coding with Verilog
Strong SystemVerilog experiences.
Strong C/C++ software development experiences
Be good at scripting language, such as Perl, C shell, Ruby, and  Makefile.
It is a must that the candidate has one or more of the following experience/knowledge, such as X86/ARM/8051 architecture, AMBA(AXI/AHB/APB) bus, USB(3.0/2.0/1.1; SSIC/HSIC/host/device/OTG) system, NAND Flash host controller/BCH/double-data-rate interface, Universal Flash Storage, PCI-E/PCI bus, low power design, clock generation and control, SD/eMMC host controller, SATA/SAS, Legacy IPs (SPI/SMBUS/ACPI/LPC/GPIO), General connectivity IPs (I2S/I2C/UART), Ethernet, JTAG, etc.
The candidate is expected to exhibit good verbal and written communication skills in both Chinese and English, specialized knowledge plus broad technical knowledge that facilitates integrative thinking, , driving execution of quality and timely result, capability  to solve complex, novel and no-recurring problems and decision-making on critical technical areas
Hands-on lab experience is another plus, able to understand and/or use the use scopes, logic analyzers, has knowledge or skill of board-level lab debugging.
Responsibility:
The successful candidate will work with team members and apply current functional verification techniques to perform and improve pre-silicon verification quality and product Time to Market for Southbridge design. The candidate will provide the technical leadership to the DV team for the new Southbridge project. He/She should be able to work independently on various DV tasks and providing technical guidance to the DV team. The candidate would involve technically in the porting/creation of the DV environment for the new design, block and chip level test plan creation and implementation, coverage analysis, and regression cleanup.
**GFX Design Verification
Job Description:
Work on the functional verification for the most leading GPU chips in the industry: discuss with architects about the architecture, understand GPU design and verify the functional correctness for graphics features on block level, sub-system level or SoC level.
Requirements
More than 4-year work experience of verification on block level or SoC level (2 years for Sr. Eng)
Good knowledge of Graphics Pipeline/Algorithm/Application or Memory management is a must.
Proficient in C++ programming is a must
Familiar with at least one of the following language :  Verilog, System Verilog, OVM,  UVM
Willing to take challenges and learn new things, have passion about the GPU design and algorithm
Good at both Oral and written English
Good at communication and team work skills
Or:
Expert in C++ programming
8 year+ work experience in SW programming in C++
Good experience in working with NA team
**Staff Design Verification Engineer for Next Generation Interconnect IP
Job Description:
We are currently looking for Staff Engineers who will be responsible for all aspects of verification on next generation integrated interconnection fabric including IO Virtualization, PCIe, Hypertransport that is deployed in CPU & GPU. The verification work includes developing testbenches, modeling, assertions/checkers/monitors, test plan & test development, regressions, and infrastructure development. Responsibility includes participating in the pre-silicon blocks, chip, multi-chip and system level verification strategy:
- Verification of SoC level design using random methodologies – Test Planning, Implementation and Execution.
- Develop System Verilog (OVM) random sequences and methods.
- Maintain and Interface with existing random generators, models and APIs
- Integration of random modules to various testbenches.
- Executing verification through directed and random tests for its functionality and interface protocols and tracking bug reports. Creation of the needed test libraries, test API, simulation models. Debugging regression failures and identify the cause.
- Strong documentation and communication skills.
- Ability to work well in a dynamic, fast-paced, pressure filled environment, across multiple sites North America and Asia
- Flexible in terms of responsibilities and hours.
Requirement:
- 5+ years experience with Master degree or 7+ years experience with Bachelor degree.
- Complex IP/ASIC/SOC Design Verification, direct experience in IP/SOC or Processor (CPU or GPU) or Industry bus standard (PCI-e, HT, USB, DDR, DisplayPort) or multimedia/video is preferred.
- Good knowledge of SystemVerilog and OVM is a plus.
- Good knowledge of Verilog/C/C++/System C/SystemVerilog.
- Verification insights into random techniques.
- Verification of large scale ASICs.
- Experience in power verification is an asset.
- Verification of Virtualization Components is an asset.
- Strong C and C++ software development and scripting languages (Perl, C Shell, Makefile, …) experience.
- Solid background with hardware verification methodologies such as coverage-based verification methodology with the use of hardware assertions (PSL or SVA).
4. **Sr. Fro-end ASIC Design CAD engineer
Participate in the design and implementation of the leading edge, front-end ASIC design flow
Participate in the research of Design Methodology to improve automation and  productivity to produce AMD's new high-quality cutting-edge APU and GPU products
Technical support and programming
Interface with EDA vendors on technology
Essential Requirements/Qualifications:
Major in EE, CS or related, Master Degree with 3+ years or Bachelor with 5+ years working experience
Experience in Front-end digital design and VerilogHDL is required
Good programming skill with one or more languages (e.g. Tcl, Perl, python, c/c++, etc.) in Unix/Linux and a strong desire to automate flow
Familiar with SRAM design and behaviour is a plus
Familiar with one or more ASIC flows (logic synthesis, STA etc.) and usage of related EDA tools is a plus
Good written and spoken English
Good communication skills and be able to work both independently and in a team
5.** Windows/Linux 2D/3D graphics driver Senior/MTS
**D3D engneer
DESCRIPTION OF DUTIES IN ADDITION TO THOSE IN JOB DESCRIPTION:
- Develop and Maintain the AMD GPU DirectX Driver.
- Work with HW design team to tune DirectX Driver performance.
PREFERRED EXPERIENCE:
- Master/Ph.D Degree of Computer Science, Mathematics or Electronic Engineering.
- 3+ years experience working in Graphics Driver under Microsoft Windows.
- 5+ years experience of C/C++ programming.
- Knowledge of DirectX application developing under Microsoft Windows.
- Knowledge of Computer Graphics.
- Knowledge of x86 assembler language and x86/x64 CPU instructions.
- Knowledge of PC architecture.
**Senior Software Development Engineer
Windows Graphic Base Driver
ROLE & RESPOSIBILITIES
Work as part of the global base graphics engineering team to design and maintain the graphics device driver
Resolve problem reports related to graphics device driver including troubleshooting, debugging, & defect correction
Specify, design, and implement new ASIC and software features
Coordinate closely with peers at both Asia and North America to ensure timely and effective communication of all assigned work activities.
20%~50% travel time between China Mainland and Taiwan expected.
DESIRED EXPERIENCE:
Experience in multi-threaded programming in a x86 architecture in both kernel & user modes.
Object-oriented design & programming
C/C++ programming
Experience with software debugging and related tool such as WinDbg or gdb in an x86 architecture in both kernel & user modes is a plus
Min. 3 years direct experience in Windows or Linux graphics driver development is preferred
Experience in Low-level programming of hardware devices is preferred
Experience with display technologies (DisplayPort, HDMI, Stereo 3D display, wireless display, etc.) is a plus
DESIRED KNOWLEDGE, SKILLS & CHARACTERISTICS
In depth understanding of PC architecture
In depth understanding of Operating System architecture
Good software debugging logic and hands on knowledge
Good verbal and written communication skill
Excellent multi-tasking and prioritization skill
Good team works
Self motivated, strong initiative, can work under moderate to minimal supervision
EDUCATION
BA/BS degree with strong academic background or equivalent experience (higher level degree a plus) in Computer Science, Electrical Engineering, Software Engineering. MS or PHD is a plus.
**Linux Graphics 2d driver
DESCRIPTION OF DUTIES IN ADDITION TO THOSE IN JOB DESCRIPTION:
- Design, code, optimize and maintain AMD Linux graphics display driver
- AMD new graphics ASIC bring up under Linux
PREFERRED EXPERIENCE:
- Mater degree or above in C.S. or E.E.
- Good knowledge of C/C++ programming
- Good knowledge of Linux kernel programming
- Good knowledge of graphics is a plus
- Good written and verbal communication skills
- 3+ years experience in C/C++ programming
- 3+ years experience in Linux kernel development and debugging
- 3+ years experience in Linux device driver development and debugging
- Experience in graphics driver development is a plus
- Experience in XServer/X.Org development is a plus
- Fluent English language communication skills (including verbal/writing/reading), and CET-6 pass is a minimum
6.** MTS/SMTS Android Device Driver Development
Job Description:
DESCRIPTION OF DUTIES:
Provide technical leadership in the development of device driver
Closely interact with ASIC design team in new feature definition and bring up for future product generation
Architect, design and implement Android bus/device drivers and HALs for AMD ASICs
Improve customer satisfaction and product quality by fixing problems
Accountable on time delivery of deliverables
Collaborate and interface with local and global management, development and test teams to deliver a complete product solution
Regular communication via Audio/Video conference with teams in North America
PREFERRED EXPERIENCE:
BS-CS/BS-EE with at least 7 years experience in Android/Linux device driver development, or 5 years experience for master degree
Excellent and demonstrable C/C++ programming skills
Experience with programming in C/Java interface would be an asset
Experience with Linux kernel mode driver programming under Android/Linux environment.
Experience with USB, SD, network, camera/ISP, A/V stream, power management, etc. driver development preferred
Experience with PCI/PCI-E/AMBA/MIPI/I2C device driver development required
Good understanding of embedded system and/or tablet architecture is a plus
Strong analysis and problem solving skills required
Proven interpersonal skill, technical leadership and teamwork required
Must be fluent in both written and spoken English
Experience working with multi-site teams preferred
7. ** MTS/SE for Camera/ISP SW Development (Android)
PREFERRED EXPERIENCE:
BS-CS/BS-EE with at least 7 years’ experience in Android/Linux device driver development, or 5+ years’ experience for MS
Good at ARM assembly and C/C++ language,  demonstrable C/C++ programming skills
Experience with Android camera HAL, camera service programming.
Experience with Android multimedia OpenMAX framework integration.
Experience with Android kernel V4L2, camera sensor, VCM and flash driver programming.
Experience with ISP, camera sensor tuning activity.
Good understanding of embedded system and/or tablet architecture is a plus
Strong analysis and problem solving skills required
Proven interpersonal skill, technical leadership and teamwork required
Fluent in both written and spoken English
- Experience of working with multi-site teams preferred
KEY Responsibilities:
Architect, design and implement Linux/Android Camera/ISP solutions for AMD Platform Solutions
Closely interact with ASIC design team in new feature definition and bring up for future product generation
Improve customer satisfaction and product quality by solving technical problems
Accountable on time delivery of deliverables
Collaborate and interface with local and global management, development and test teams to deliver a complete product solution
Regular communication via Audio/Video conference with global teams
8. **Open GL MTS JD
DESCRIPTION OF DUTIES
- Implement OpenGL new features for new generation Graphic chips.
- Improve OpenGL benchmark performance.
- Work with key customers and vendors for implementation and issue solving.
- Interact with the Graphics Community .
Develop internal tools to improve development efficiency.
PREFERRED EXPERIENCE:
- Solid knowledge in C/C++ programming language, at least 5 years plus C/C++ language experience.
- Solid knowledge in Computer Graphics.
- Strong knowledge in Linux kernal, 1 year plus Linux development experience
- Strong knowledge in software development life cycle.
- Strong knowledge in debug tools usage.
- High quality team player as good team working spirits and easy going with team members.
- Prefer MS or higher education in CS or EE or Mathematic.
9. **Principle/Senior Staff Design Architect for 10GE+ IP
Own IP architecture definition, derive functional and design specifications and analyze feasibility of technical and architectures.
Discuss with SW architect to generate an optimized HW/SW partition of the system architecture
Guide the design team to implement design with Verilog to achieve specification goals. Simulate and debug the codes in coding stage.
Support the Front-End Integration team to deliver qualified netlist. Feedback to Physical Design team to help to close timing and check floorplan.
Support FW/SW bring-up and debugging
Working as the overall technical expert of contact on the 10GE area.
Essential Functions:
Architecture, Algorithm, RTL, Performance modeling
Essential Requirements:
Rich Experience in 10GE+ IP solution, including HW IP and SW stack
Deep understanding of
10GbE+ solutions from the industry leading companies
basic offload engines used in 10GbE/40GbE, such as
TCP transmit segmentation offloading
TCP Large receive offload
Receive side scaling
Basic filtering and Classification: Unicast/multicast/broadcast, ACLs
Advanced filtering and classification: flow based and L3 protocol based
Data-center bridging, PFC/ETS/DCBX/QCN
Device virtualization, SR-IOV/VEB/VEPA
Advanced offload engine
TCP offload: TOE
Storage offload: iSCSI HBA/FCoE HBA
RDMA: RoCE/iWARP
Security offload: IPSec
PHY interfaces
Good English hearing, speaking, reading and writing capabilities
Good communication skills
Have mass production tape‐out experience
Should have strong problem solving skills
**Senior Staff/Staff Design Lead for Wired Connection IP
Participate IP and SoC level architecture definition, create IP architectural spec, derive functional and design specifications and analyze feasibility of technical and architectures.
Implement design with Verilog to achieve specification goals. Simulate and debug the codes in coding stage.
Define timing constraints and support the FE Integration team to deliver qualified netlist. Feedback to Physical Design team to help to close timing and check floorplan
Discuss with SW team to generate an optimized HW/SW partition of the functionalities
Support FW/SW bring-up and debugging
Working as the technical point of contact in the Wired Connection IP area.
Maintain design environment, solve flow issues, and develop scripts to improve flow efficiency.
Essential Functions:
Architecture, RTL, Synthesis, STA, Timing Analysis, Constraints
Essential Requirements/Qualifications:
Proven IP / SoC Design / Integration Experience
Must have strong background on IP development
Desired:
       Enthusiasm on technical topics
       Major in EE & CS
       Must be proficient in Verilog coding, debugging and modeling
       Deep understanding of below technical aspects would be an asset:
10GbE+ solutions from the industry leading companies
basic offload engines used in 10GbE/40GbE, such as
TCP transmit segmentation offloading
TCP Large receive offload
Receive side scaling
Basic filtering and Classification: Unicast/multicast/broadcast, ACLs
Advanced filtering and classification: flow based and L3 protocol based
Data-center bridging, PFC/ETS/DCBX/QCN
Device virtualization, SR-IOV/VEB/VEPA
Advanced offload engine
TCP offload: TOE
Storage offload: iSCSI HBA/FCoE HBA
RDMA: RoCE/iWARP
Security offload: IPSec
- 10 gigabit+ Ethernet IP design experience would be an asset
Ethernet HW/SW performance analysis experience would be an asset
Be familiar with ASIC design flow, such as synthesis, DFT, timing analysis, ECO etc
Be familiar with shell/perl/tcl programming in linux OS.
Should have strong problem solving skills
Good English hearing, speaking, reading and writing capabilities
Good communication skills
Have mass production tape‐out experience