I have a problem with ahdl9.1 assertion. Each time i have a small SV assertion in my simulation we got an error like this:
# ELBREAD: Error: You do not have a valid license to simulate SystemVerilog assertion module 'test1.propseq_assertion'.
# Contact Aldec for ordering information - sales@aldec.com.
# ELBREAD: Error: Elaboration process completed with errors.
# Design: Error: Elaboration failed
Is there any license for assertion based simulation in HDL? Or i am looking for some thing invalid!!!