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NVIDIA现有DFT/PD/PR 职位空缺,比较紧急,有意愿的可以发简历到lgao@nvidia.com,标题注明职位。希望相对较大呦PHYSICAL DESIGN ENGINEERDESCRIPTION:A challenging role in physical design for all NVIDIA GPU and Mobile chips, including full chip floorplanning, power/clock distribution, timing optimization, place & route, timing closure, power/signal integrity analysis, and physical verification. Participate in developing methodologies, flow automation and improvements. Opportunity to work with the RTL and Circuit designers to ensure the design is balanced and optimized among physical, RTL, Circuit specifications.MINIMUM REQUIREMENTS:- BS in Engineering or Science- Power user of EDA tools from Synopsys (ICC/DC/PT/STAR-RC), Cadence (EDI/EPS) or Mentor (Olympus-SOC)- Experience in Clock/Power Distribution, P&R, Timing closure, RC Extraction, and verification on 65nm, 40nm, or 28nm technology- 2+ years of experience in above areasPREFERRED:- MS in Engineering or Science- Experience in physical verification tools from Synopsys (ICV/Mojave) or Mentor (Calibre)- Proficiency in Perl, TCL and Makefile scriptsJob Title: DFT Engineer (Junior-At least 2yrs’ DFT experience/Senior-At least 4yrs’ relative experience)Department: GPULocation: ShanghaiJob Description/Qualifications:Responsibilities:• Responsible for DFT implementation including test mode controllers, Memory BIST/Repair and JTAG based on DFT plan.• Responsible for scan insertion, ATPG and post silicon validation.• Responsible for DFT logic and pattern verification.• Responsible for ATE chip bringup and failure analysis.Minimum Requirement:• BSEE required, MSEE preferred. • 3+ years of experience in DFT/design field• Strong logic Design and verification background with experience in STA.• Must possess a strong knowledge of DFT including scan, ATPG, Test Compression, JTAG and BIST.• Programming in Perl, tcl and C/C++ is a plus• Good Englisth communication skills• Self-motivated and good team player |
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