Cadence SH 招聘资深数字后端设计工程师 & 数字前端验证工程师

kengteng

Cadence SH 招聘资深数字后端设计工程师 & 数字前端验证工程师

If you haveinterest, PLS send your update CV to zhangyl@cadence.com

Title：Principal Physical design Engineer

PositionDescription:

The candidates should be senior in a way thatthey are not only technical excellent but also mature & able to communicatewith customers, following team members. This engineer should have excellentdesign experiences in the digital implementation domain including Floorplan,P&R, STA, Physical verification, DFM. The engineer must have a solidbackground in circuits, electronics & physics & should be very willingto learn new stuff.

1. Ability to handle large sized designimplementation tasks & architectural tasks alone.

2. Ability to assess Customer's Designenvironment, to understand his application needs & to build new Designenvironment based on specifications & available Cadence tool technology.

3. Ability to acquire a basic understanding ofthe (services) business environment of Cadence within 1 month. Working on multiperson projects of varying complexity, working especially in amulti-site/multi-cultural project.

4. Good communication skills in English. Feel responsiblefor technical delivery as well as business development & opportunitycreation.

5. Behavioral competencies: Teamwork; Customerfocus; Accountability; Communication; Coaching & feedback; Employeedevelopment; Leadership.

PositionRequirements:         

1. Must have BS degree with 15+ years ofapplicable experience, MS degree with 10+ years of applicable experience inelectrical engineering, microelectronics.

2. Essential that the individual demonstratesstrong communication, verbal and written, and project management skills.

3. Requires good communication skills inEnglish.

Title：Principal Verification Engineer

                           

Position Description:               

Deliver/implementadvanced verification solutions by utilizing Cadence’s Incisive Verificationproduct portfolio. The engineer should be able to act as a strong team memberand contributor, leading team projects and initiatives. Exercise judgmentwithin generally defined practices and policies.

Specific duties include:

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Deep understanding on ASIC/SOCdesign flow

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Excellent knowledge of advancedverification methodology like eRM/OVM/UVM

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Familiar with Cadence’s IncisivePlan to Closure Methodology (IPCM)

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Proficiency in SystemVerilog,  System C and/or e (Specman)

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Developing and using VerificationComponents (eVC, OVC, UVC, VIP)

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Developing and using assertionbased verification and formal analysis methods

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Skilled in scripting language,such as Perl, C shell, Makefile

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Assessing the projectverification requirements

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Operating in a lead roleregarding architecting and implementation of project verificationenvironment/solution.

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May coordinate/lead others withinthe scope of a defined project

Position Requirements:               

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Have BS degree with 7~10 years ofapplicable experience, MS degree with 4~7 years of applicable experience inelectrical engineering, microelectronics, comparable engineering science orsolid state physics.

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Requires good communication skillsin English.

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A minimum of seven years relevantexperience in industry.

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Will have demonstrated hands-onexperience and expertise with Cadence verification design tools or equivalenttools, flows and methodologies required to execute a verification project.

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Will have demonstrated successfulcompletion of 10+ verification projects as an individual contributor

wangjunweiair

帮顶一个

heidong123

Cadence 是一家优秀的公司，就是招人要求好高啊，我这种3年的入门级，直接都不符合条件