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littleyard · 发表于 2007-1-17 14:05:59

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Key Responsibilities:

Ø    Architecture design and logic implementation, simulation and functional verification
Ø    HW and SW partition and related interface design
Ø    Detailed, functional HW Design Document, originating from the requirement specs.
Ø    C Model Design based on the Architecture and related specification document.
Ø    Scope out the effort required for a particular implementation in Hardware (FPGA, ASIC, SoC integration, etc).
Ø    Independently work on a bounded functional module and take it through the VLSI front end design flow (RTL Coding, Functional simulation, Functional verification, synthesis and timing closure)
Ø    Interact with the clients and provide periodic (weekly) status on the progress and update of any issues in the project that would prevent us from being on schedule.

Education, Skill and Experience Requirement:
Ø    Bachelors/Masters degree in Electronics/Computer Science
Ø    4+ years of ASIC/FPGA/SoC design expertise in front end

Ø    Detailed working knowledge of the various Video coding standards, i.e. MPEG-1, MPEG-2, MPEG-4, H.261, H.263, H.264 and AVS
Ø    Proficiency in Verilog and C, Perl or TCL is a plus
Ø    Good at EDA tools from Cadence, Synopsys and Mentor, experience in C to RTL tool is a plus
Ø    Familiar with FPGA/ASIC design flow, ASIC synthesis and 130/90nm technologies
Ø    Experienced in Video related design and verification, SoC design is a plus
Ø    Fluent in oral and written English with good communication skills
Ø    Has worked in teams spread across multiple locations. Able to co-ordinate with off site development teams

有意者发邮件到：linda@consulting-wireless.com

[ 本帖最后由 littleyard 于 2007-2-1 17:52 编辑 ]