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Hi, All
Does anyone get Mbistarchitect run Dual Port ram simulation issue ?
below is my RTL simulation(NC-Verilog) message.
** MEM_Warning: Read and Write the same Address, DO is unknown ( 1300000 ps) in clock of BistController_SHTD110_128X25X1CM2_tb.E1.mem_block_SZTD110_128X25X1CM2_instance_0.SZTD110_128X25X1CM2_instance_0.ErrorMessage
## below is my MBIST dofile.
reset state -all
load library ../SZTD110_128X25X1CM2.mbist
add memory model SZTD110_128X25X1CM2
set bist insertion -on
set controller delay 1
setup memory clock -test invert
set design name Controller -module BistController_SHTD110_128X25X1CM2
set design name Collar -module mem_block
set file naming -bist_model MBIST_SHTD110_128X25X1CM2.v
set file naming -connected_model MBIST_SHTD110_128X25X1CM2_con.v
set file naming -test_bench MBIST_SHTD110_128X25X1CM2_tb.v
set file naming -script MBIST_SHTD110_128X25X1CM2.dcscript
set file naming -ctdl MBIST_SHTD110_128X25X1CM2.v_ctdf
set file naming -wgl MBIST_SHTD110_128X25X1CM2.v_wgl
set write files -gate single_file
set scan logic
run
save bist -verilog -script -replace
report mbist algorithms
exit
## *.mbist library as below.
model SZTD110_128X25X1CM2 (
A6, A5, A4, A3, A2, A1, A0,
B6, B5, B4, B3, B2, B1, B0,
DI24, DI23, DI22, DI21, DI20, DI19, DI18, DI17, DI16, DI15, DI14, DI13, DI12, DI11, DI10, DI9, DI8, DI7, DI6, DI5, DI4, DI3, DI2, DI1, DI0,
DO24, DO23, DO22, DO21, DO20, DO19, DO18, DO17, DO16, DO15, DO14, DO13, DO12, DO11, DO10, DO9, DO8, DO7, DO6, DO5, DO4, DO3, DO2, DO1, DO0,
WEB,
CKA, CKB, CSAN, CSBN) (
bist_definition (
data_out DO (DO24, DO23, DO22, DO21, DO20, DO19, DO18, DO17, DO16, DO15, DO14, DO13, DO12, DO11, DO10, DO9, DO8, DO7, DO6, DO5, DO4, DO3, DO2, DO1, DO0);
data_in DI (DI24, DI23, DI22, DI21, DI20, DI19, DI18, DI17, DI16, DI15, DI14, DI13, DI12, DI11, DI10, DI9, DI8, DI7, DI6, DI5, DI4, DI3, DI2, DI1, DI0);
address A (A6, A5, A4, A3, A2, A1, A0);
address B (B6, B5, B4, B3, B2, B1, B0);
write_enable WEB low;
chip_enable CSAN low;
chip_enable CSBN low;
clock CKA high;
clock CKB high;
tech = FSR0T_D;
vendor = "Faraday Technology Inc.";
version = "201001.1.4";
min_address = 0;
max_address = 127;
data_size = 25;
top_column = 2;
top_word = 1;
descrambling_definition (
address (
DSC_A0 = A0;
DSC_A1 = A1;
DSC_A2 = A2;
DSC_A3 = A3;
DSC_A4 = A4;
DSC_A5 = A5;
DSC_A6 = A6;
)
)
read_port(
read_cycle(
assert CSAN;
change A;
expect DO move;
)
)
write_port(
write_cycle(
assert CSBN;
change B;
change DI;
assert WEB;
wait;
)
)
)
) |
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