|
|
马上注册，结交更多好友，享用更多功能，让你轻松玩转社区。
您需要 登录 才可以下载或查看，没有账号？注册
x
I met a problem about writing a spf.
1. During the initial stage, the test clock pin is required to set at 1'b1 for serving as a control signal (like reset), and then become to 1'b0 after a period of 5000ns.
2. After the reset is done, the test mode can only be triggered by a sequence of control inputs. And then the clock can be pulsed to start the scanning.
I tried to use V { "clk" = 1} in "test_setup" section to force the clk is in high state during the beginning. But the tetramax complains errors that "clk" should be pulsed, not forced on.
How can I write such spf for tetramax?
Thx a lot. |
|
/1 
eetop公众号
创芯大讲堂
创芯人才网
发表于 2013-4-25 16:46:11
