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本帖最后由 Jason.tschen 于 2013-4-25 09:42 编辑
High-Speed Signaling: Jitter Modeling, Analysis, and Budgeting
Kyung Suk (Dan) Oh (Author), Xing Chao (Chuck) Yuan (Author)
Hardcover: 528 pages
Publisher: Prentice Hall; 1 edition (October 16, 2011)
Language: English
ISBN-10: 0132826917
ISBN-13: 978-0132826914
本书当然是扫瞄版......
基于爱护地球及环保 , 本书不欢迎列印 , 仅供阅读.....
基于爱护辛勤劳动者 , 不欢迎转贴.....
更不欢迎流出EETOP又流回EETOP.....
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Table of Contents
Chapter 1: Introduction
Section 1.1. Signal Integrity Analysis Trends
Section 1.2. Challenges of High-Speed Signal Integrity Design
Section 1.3. Organization of This Book
Chapter 2: High-Speed Signaling Basics
Section 2.1. I/O Signaling Basics and Components
Section 2.2. Noise Sources
Section 2.3. Jitter Basics and Decompositions
Section 2.4. Summary
Part I: Channel Modeling and Design
Chapter 3: Channel Modeling and Design Methodology
Section 3.1. Channel Design Methodology
Section 3.2. Channel Modeling Methodology
Section 3.3. Modeling with Electromagnetic Field Solvers
Section 3.4. Backplane Channel Modeling Example
Section 3.5. Summary
Chapter 4: Network Parameters
Section 4.1. Generalized Network Parameters for Multi-Conductor Systems
Section 4.2. Preparing an Accurate S-Parameter Time-Domain Model
Section 4.3. Passivity Conditions
Section 4.4. Causality Conditions
Section 4.5. Summary
Chapter 5: Transmission Lines
Section 5.1. Transmission Line Theory
Section 5.2. Forward and Backward Crosstalk
Section 5.3. Time-Domain Simulation of Transmission Lines
Section 5.4. Modeling Transmission Line from Measurements
Section 5.5. On-Chip Wire Modeling
Section 5.6. Comparison of On-Chip, Package, and PCB Traces
Section 5.7. Summary
Part II: Analyzing Link Performance
Chapter 6: Channel Voltage and Timing Budget
Section 6.1. Timing Budget Equation and Components
Section 6.2. Fibre Channel Dual-Dirac Model
Section 6.3. Component-Level Timing Budget
Section 6.4. Pitfalls of Timing Budget Equation
Section 6.5. Voltage Budget Equations and Components
Section 6.6. Summary
Chapter 7: Manufacturing Variation Modeling
Section 7.1. Introduction to the Taguchi Method
Section 7.2. DDR DRAM Command/Address Channel Example
Section 7.3. Backplane Link Modeling Example
Section 7.4. Summary
Chapter 8: Link BER Modeling and Simulation
Section 8.1. Historical Background and Chapter Organization
Section 8.2. Statistical Link BER Modeling Framework
Section 8.3. Intersymbol Interference Modeling
Section 8.4. Transmitter and Receiver Jitter Modeling
Section 8.5. Periodic Jitter Modeling
Section 8.6. Summary
Chapter 9: Fast Time-Domain Channel Simulation Techniques
Section 9.1. Fast Time-Domain Simulation Flow Overview
Section 9.2. Fast System Simulation Techniques
Section 9.3. Simultaneous Switching Noise Example
Section 9.4. Comparison of Jitter Modeling Methods
Section 9.5. Peak Distortion Analysis
Section 9.6. Summary
Chapter 10: Clock Models in Link BER Analysis
Section 10.1. Independent and Common Clock Jitter Models
Section 10.2. Modeling Common Clocking Schemes
Section 10.3. CDR Circuitry Modeling
Section 10.4. Passive Channel JIF and Jitter Amplification
Section 10.5. Summary
Part III: Supply Noise and Jitter
Chapter 11: Overview of Power Integrity Engineering
Section 11.1. PDN Design Goals and Supply Budget
Section 11.2. Power Supply Budget Components
Section 11.3. Deriving a Power Supply Budget
Section 11.4. Supply Noise Analysis Methodology
Section 11.5. Steps in Power Supply Noise Analysis
Section 11.6. Summary
Chapter 12: SSN Modeling and Simulation
Section 12.1. SSN Modeling Challenges
Section 12.2. SI and PI Co-Simulation Methodology
Section 12.3. Signal Current Loop and Supply Noise
Section 12.4. Additional SSN Modeling Topics
Section 12.5. Case Study: DDR2 SSN Analysis for Consumer Applications
Section 12.6. Summary
Chapter 13: SSN Reduction Codes and Signaling
Section 13.1. Data Bus Inversion Code
Section 13.2. Pseudo Differential Signaling Based on 4b6b Code
Section 13.3. Summary
Chapter 14: Supply Noise and Jitter Characterization
Section 14.1. Importance of Supply Noise Induced Jitter
Section 14.2. Overview of PSIJ Modeling Methodology
Section 14.3. Noise and Jitter Simulation Methodology
Section 14.4. Case Study
Section 14.5. Summary
Chapter 15: Substrate Noise Induced Jitter
Section 15.1. Introduction
Section 15.2. Modeling Techniques
Section 15.3. Measurement Techniques
Section 15.4. Case Study
Section 15.5. Summary
Chapter 16: On-Chip Link Measurement Techniques
Section 16.1. Shmoo and BER Eye Diagram Measurements
Section 16.2. Capturing Signal Waveforms
Section 16.3. Link Performance Measurement and Correlation
Section 16.4. On-Chip Supply Noise Measurement Techniques
Section 16.5. Advanced Power Integrity Measurements
Section 16.6. Summary
Chapter 17: Signal Conditioning
Section 17.1. Single-Bit Response
Section 17.2. Equalization Techniques
Section 17.3. Equalization Adaptation Algorithms
Section 17.4. CDR and Equalization Adaptation Interaction
Section 17.5. ADC-Based Receive Equalization
Section 17.6. Future of High-Speed Wireline Equalization
Section 17.7. Summary
Chapter 18: Applications
Section 18.1. XDR: High-Performance Differential Memory System
Section 18.2. Mobile XDR: Low Power Differential Memory System
Section 18.3. Main Memory Systems beyond DDR3
Section 18.4. Future Signaling Systems |
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发表于 2013-4-25 09:41:22
