Cadence SH 招聘Principal/Lead/Senior PVS PE

kengteng

Cadence SH 招聘Principal/Lead/SeniorPVS PE

If you haveinterest, PLS send your CV to zhangyl@cadence.com

Title: Principal/Lead/Senior PVS Product Engineer

PositionDescription:

The Product Engineering team works withCustomers and foundries, R&D, Marketing, and the Field ApplicationsEngineers to create products that address the unique and complex needs of ourcustomers. A Physical Verification Product Engineer provides in-depth technicalexpertise in writing Physical Verification rule decks (i.e. DRC, ERC, FILL and LVS)and the usage of Physical Verification tools throughout physical implementationand signoff verification cycles.

Responsibilities:

Develop Physical Verification rule decks (i.e.DRC, ERC, FILL and LVS)

Setup efficient flows to improve rule deckdevelopment quality and product performance.

Run expert-level benchmarks and solve complexcustomer problems.

Work with the RD, field, customers andfoundries to identify and define product requirement and enhancement

PositionRequirements:         

Knowledge of developing rule decks forcommercial physical verification tools (e.g. PVS, Calibre, Hercules, Dracula,Assura, etc.) is required.

Experience in the following areas:

- DRC, includes density, antenna, etc.

- LVS, includes device extraction, parametermeasurement, connect/stamp sequences, short isolation, etc.

- Knowledge of netlist formats SPICE, CDL,Verilog, etc.

- DFM, includes yield analysis, via insertion,OPC, FILL, etc.

Experience with layout implementation tools(e.g. Virtuoso, DesignREV, ICStation, etc.) for the creation of qualificationcells is required.

Knowledge of automating test suites for thequalification of rule decks is a plus.

Programming of Tcl, Perl, and Skill are a plus

EDUCATION: BS or MS in Electrical Engineering.

kengteng

亲们，职位还在招聘中，以下是另外一个部门PVS相关的职位，感兴趣的同学请投简历至cecilyl@cadence.com

Senior Product Engineer - PVS

Position Description:
1.        Focus on PVS physical verification solutions.
2.        Responsible for integrating Cadence PVS into Cadence reference flows, for high-speed and advanced node designs (20nm/16nm).
3.        Work on DRC correlation between digital implementation tool and PVS, to achieve better QoR in digital implementation.
4.        Work on physical verification solutions, including DRC and LVS for various designs from block level full-chip designs of million gates.
5.        Provide technical consultant to foundry customers about Cadence PVS relevant solutions in design implementation and signoff cycles.
  
Position Requirements:
1.        Bachelor's degree with 5+ years experience or master’s degree with 2.5+ year’s experiences in IC design.
2.        In-depth expertise in physical verification among various scales of designs including both analog and digital.
3.        In-depth knowledge of DRC and LVS methodology.
4.        Working experience in multi-nation IC design house is preferred.
5.        Good communication in English and Chinese, team-spirit, self-motivated.

Senior Product Engineer for QRC

Position Description:
1.        Focus on QRC advanced solutions.
2.        Responsible for integrating Cadence QRC into Cadence reference flows, for high-speed and advanced node designs (20nm/16nm).
3.        Work on parasitic RC correlation and timing correlation between digital implementation tool and signoff tool, for better QoR.
4.        Work on PVS-QRC solutions in both digital and analog design flows.
5.        Provide in-depth technical consultant to foundry customers about Cadence digital signoff solutions, and usage of Cadence QRC in digital implementation and signoff cycles.

  Position Requirements:
1.        Bachelor's degree with 5+ years experience or master’s degree with 2.5+ year’s experiences in IC design.
2.        In-depth knowledge in parasitic RC extraction methodology, accuracy analysis and correlation, and so on.
3.        In-depth expertise in extraction tools among various scales of designs, especially at advanced nodes.
4.        Hands-on experiences in RTL-to-GDSII design projects, for designs from 500MHz to several GHz big chips.
5.        Working experience in multi-nation IC design house is preferred.
6.        Good communication in English and Chinese, team-spirit, self-motivated.