上海-招聘ASIC设计工程师

logan95

国内某顶尖通讯芯片设计公司-上海

ASIC Digital Design Engineer
1. Responsible for logic design and verification in low-power wireless communications chips.
2. Also responsible for module-level lint checking, timing checking and formal verification.

1. Proficiency in logic design, simulation, synthesis and testing.
2. Proficiency in Verilog and its simulation environment.
3. Experience with low-power design.
4. Good knowledge of SOC design.
5. Experience in wireless communication or multimedia technologies is a plus.
6. Experience in ARM and AMBA design is a plus.
7. Self-motivated and good team player.

有兴趣的发邮件或加MSN：cms020619@yahoo.com.cn

清月山风

你的邮箱是多少？

liu_uestc

能留个qq聊聊么? myqq: 2492202119