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本帖最后由 txws007 于 2013-3-21 19:27 编辑
下面是我的代码，一运行就出现Error (10200): Verilog HDL Conditional Statement error at test2.v(34): cannot match operand(s) in the condition to the corresponding edges in the enclosing event control of the always construct这个错误，这是什么意思？
module hm(clk,rst_n,data,pulse,key/*,load*/); input clk,rst_n,key; input [7:0] data; output pulse/*,load*/; reg [7:0] count; reg pulse; reg clk_1; reg [4:0] a; always @(posedge clk or negedge rst_n) begin if(~rst_n) begin
clk_1=0;
a<=5'd0;
end
else
if(a==5'd16)
begin
a<=5'd0;
clk_1=~clk_1;
end
else
a<=a+5'd1;
end always @(posedge clk_1 or negedge rst_n) begin
if(~rst_n)
begin
count<=0;
pulse<=0;
end
else
count<=data;
if(key==0)
begin
pulse<=1;
count<=count-8'd1;
if(count==8'd0)
begin
pulse<=0;
count<=8'd0;
if(pulse==0)
begin
count<=data;
end
end
end
end
endmodule | 
/2 
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发表于 2013-3-20 19:52:10
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